A semiconductor device includes a first plurality of channel layers. The first plurality of channel layers extend along a first direction. The semiconductor device includes a second plurality of channel layers. The second plurality of channel layers also extend along the first direction. The semiconductor de123329-vice includes a first dielectric fin structure that also extends along the first direction. The semiconductor device includes a first gate structure that extends along a second direction. The first gate structure comprises a first portion that wraps around each of the first plurality of channel layers and a second portion that wraps around each of the second plurality of channel layers. The first dielectric fin structure separates the first and second portions from each other. The first gate structure comprises a third portion that connects the first and second portions to each other and is vertically disposed below the first dielectric fin structure.

Embodiments include plating a contact feature in a first opening in a mask layer, the contact feature physically coupled to a contact pad, the contact feature partially filling the first opening. A solder cap is directly plated onto the contact feature in the first opening. The mask layer is then removed to expose an upper surface of a work piece, the contact feature vertically protruding from the work piece. After utilizing the solder cap, etching the solder cap to remove the solder cap from over the contact feature. A first encapsulant is deposited laterally around and over an upper surface of the contact feature. The first encapsulant is planarized to level an upper surface of the first encapsulant with the upper surface of the contact feature.

Provided are: a semiconductor treatment liquid containing a hypobromite ion, in which the concentration of the hypobromite ion is 0.1 μmol/L or more and less than 0.001 mol/L; a RuO.sub.4 gas generation inhibitor containing an onium salt composed of an onium ion and a bromine-containing ion, in which the hypobromite ion concentration is 0.1 μmol/L or more and less than 0.001 mol/L; and a method of producing a halogen oxyacid, the method including allowing a bromine salt, an organic alkali, and a halogen to react with each other to obtain the halogen oxyacid.

A method of manufacturing a semiconductor package, the method including providing a first seed layer on an insulation layer such that the first seed layer includes a first metal material; providing a second seed layer on the first seed layer such that the second seed layer includes a second metal material different from the first metal material; forming photoresist patterns on the second seed layer; forming conductive patterns between the photoresist patterns, including the second metal material, and having line shapes that extend in a first direction; removing the photoresist patterns; etching the second seed layer to form second seed patterns having line shapes extending in the first direction; and etching the first seed layer to form first seed patterns having line shapes extending in the first direction, wherein an etchant includes deionized water, a fluorine compound, a competing compound, and a corrosion inhibitor.

A manufacturing method of a semiconductor structure includes the following operations. A stacked structure is formed on a substrate. The stacked structure includes semiconductor layers and sacrificial layers that are alternately stacked, in which the sacrificial layers include germanium, and germanium concentrations of the sacrificial layers decrease from bottom to top. A dummy gate structure is formed on the stacked structure. A spacer is formed on both sides of the dummy gate structure. The dummy gate structure is removed, thereby forming an opening. The sacrificial layers are removed from the opening. A gate structure is formed to cover the semiconductor layers. In another manufacturing method, the stacked structure includes semiconductor layers and sacrificial layers that are alternately stacked, in which thicknesses of the semiconductor layers increase from bottom to top, or thicknesses of the sacrificial layers increase from bottom to top.

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

A display substrate, a manufacturing method thereof, a display panel, and a display device are provided. The method for manufacturing a display substrate includes: forming a thin film transistor on a base substrate; forming a planarization layer covering the thin film transistor; forming a metal mask layer on the planarization layer; patterning the metal mask layer to form an etching hole in the metal mask layer, the etching hole exposing a portion of the planarization layer; etching the portion of the planarization layer exposed by the etching hole to form a first via hole penetrating the planarization layer, and removing a remaining metal mask layer on the planarization layer.

A silicon etching solution includes a mixed solution comprising a quaternary alkylammonium hydroxide and water and further comprises a compound represented by the following formula (1):
R.sup.1O—(C.sub.mH.sub.2mO).sub.n—R.sup.2  (1)
wherein R.sup.1 is a hydrogen atom or an alkyl group having 1 to 3 carbon atoms, R.sup.2 is a hydrogen atom or an alkyl group having 1 to 6 carbon atoms, m is an integer of 2 to 6, and n is 1 or 2.

In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.

A substrate processing method includes etching a substrate having a first film and a second film at a first etching rate; changing an etching rate from the first etching rate to a second etching rate; and etching the substrate at the second etching rate.