Systems and methods herein are related to the formation of optical devices including stacked optical element layers using silicon wafers, glass, or devices as substrates. The optical elements discussed herein can be fabricated on temporary or permanent substrates. In some examples, the optical devices are fabricated to include transparent substrates or devices including charge-coupled devices (CCD), or complementary metal-oxide semiconductor (CMOS) image sensors, light-emitting diodes (LED), a micro-LED (uLED) display, organic light-emitting diode (OLED) or vertical-cavity surface-emitting laser (VCSELs). The optical elements can have interlayers formed in between optical element layers, where the interlayers can range in thickness from 1 nm to 3 mm.

An apparatus for perform metal etching and plasma ashing includes: a processing chamber having an enclosed area; an electrostatic chuck disposed in the enclosed area and configured to secure a wafer, the electrostatic chuck connected with a bias power; at least one coil connected with a source power; a etchant conduit configured provide an etchant to a metal of the wafer within the processing chamber in accordance with a photoresist mask of the wafer; and a gas intake conduit connected with a gas source, wherein the gas intake conduit is configured to supply the processing chamber with a gas from the gas source during performance of plasma ashing within the processing chamber.

A multilayer conductive line is disclosed. The multilayer conductive line includes a dielectric layer, a Ta barrier layer on the dielectric layer and a superlattice on the Ta barrier layer. The superlattice includes a plurality of interleaved ferromagnetic and non-ferromagnetic material.

A treatment liquid for a semiconductor containing a group 6 metal, the treatment liquid containing hypobromite ions. Also provided is a treatment liquid for a semiconductor containing a group 6 metal, the treatment liquid characterized by being formed by adding and mixing at least a bromine-containing compound, an oxidizing agent, a base compound, and water, wherein relative to a total mass, an added amount of the bromine-containing compound is 0.008 mass % or more and less than 10 mass % as an amount of bromine element, and an added amount of the oxidizing agent is 0.1 mass ppm or more and 20 mass % or less; and pH at 25° C. is 8 or higher and 14 or lower. Further provided is a method for producing the treatment liquid for a semiconductor.

A process for forming cobalt on a substrate, comprising: volatilizing a cobalt precursor of the disclosure, to form, a precursor vapor: and contacting the precursor vapor with the substrate under vapor deposition conditions effective for depositing cobalt on the substrate from the precursor vapor, wherein the vapor deposition conditions include temperature not exceeding 200° C., wherein: the substrate includes copper surface and dielectric material, e.g., ultra-low dielectric material. Such cobalt deposition process can be used to manufacture product articles in which the deposited cobalt forms a capping layer, encapsulating layer, electrode, diffusion layer, or seed for electroplating of metal thereon, e.g., a semiconductor device, flat-panel, display, or solar panel. A cleaning composition containing base and oxidizing agent components may be employed to clean the copper prior to deposition of cobalt thereon, to achieve substantially reduced defects in the deposited cobalt.

The invention provides a method for forming a semiconductor structure. The method includes providing a substrate, forming a gate structure on the substrate, respectively forming an epitaxial layer on both sides of the gate structure, and performing a pre-amorphization doping step on the substrate. After the pre-amorphization doping step, a defect is generated in the epitaxial layer, an outer spacer is formed beside the gate structure, and a chemical cleaning step is performed to remove a part of the epitaxial layer, and the defect in the epitaxial layer is removed.

Methods for manufacturing semiconductor structures are provided. The method for manufacturing the semiconductor structure includes forming a fin structure protruding from a substrate and forming a source/drain structure over the fin structure. The method for manufacturing a semiconductor structure further includes forming a metallic layer over the source/drain structure and forming an oxide film on a sidewall of the source/drain structure. In addition, the oxide film and the metallic layer are both in direct contact with the source/drain structure.

The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.

A method for fabricating a semiconductor device includes: forming a first gate dielectric layer in a first and a second regions of a peripheral region of a substrate; forming a first conductive layer and a first hard mask layer over the substrate; forming a first mask layer on the first hard mask layer in the first region; removing the first hard mask layer outside the first region; removing the first hard mask layer; performing a wet etch process by taking the first hard mask layer as a mask, and removing the first conductive layer and the first gate dielectric layer outside the first region; removing the first hard mask layer and the first conductive layer; forming a second gate dielectric layer in the second region; and forming a first and a second gate conductive layers in the first and the second regions respectively.

A method includes forming a dummy gate electrode on a semiconductor region, forming a first gate spacer on a sidewall of the dummy gate electrode, and removing an upper portion of the first gate spacer to form a recess, wherein a lower portion of the first gate spacer remains, filling the recess with a second gate spacer, removing the dummy gate electrode to form a trench, and forming a replacement gate electrode in the trench.