A method of preparing an air gap includes: forming a first covering layer etching and removing part higher than a horizontal line where a top of the oxide layer is located; forming a first oxide layer on an etched plane; etching the first oxide layer; removing a part of the first oxide layer; reserving a rest part of the first oxide layer; taking a reserved first oxide layer as an oxide layer pattern; forming a second covering layer at a position of a removed part of the first oxide layer; removing the oxide layer pattern and the oxide layer.

A metal removal method which includes: a reaction step of bringing a treatment gas containing a fluorine-containing interhalogen compound and a metal-containing material containing a metal element into contact with each other to generate metal fluoride which is a reaction product of the fluorine-containing interhalogen compound and the metal element; and a volatilization step of heating the metal fluoride under an inert gas atmosphere or in a vacuum environment for volatilization. The metal element is at least one kind selected from iron, cobalt, nickel, selenium, molybdenum, rhodium, palladium, tungsten, rhenium, iridium, and platinum. Also disclosed is a dry etching method using the metal removal method and a production method for a semiconductor element using the dry etching method.

Exemplary methods of etching may include flowing a fluorine-containing precursor and a secondary gas into a processing region of a semiconductor processing chamber. The secondary gas may be or include oxygen or nitrogen. A flow rate ratio of the fluorine-containing precursor to the secondary gas may be greater than or about 1:1. The methods may include contacting a substrate with the fluorine-containing precursor and the secondary gas. The substrate may include an exposed metal. The substrate may define a high aspect-ratio structure. The methods may include etching the exposed metal within the high aspect-ratio structure.

A manufacturing method of a metal grid includes: providing a base substrate; forming a pattern including a first dielectric layer on the base substrate through a patterning process such that the first dielectric layer has a first groove in a lattice shape; forming a second dielectric layer on a side of the first dielectric layer away from the base substrate such that the second dielectric layer is deposited at least on a sidewall of the first groove to form a second groove in a lattice shape; and forming a metal material in the second groove, and removing at least a part of a material of the second dielectric layer such that an orthographic projection of the part of the material of the second dielectric layer on the base substrate does not overlap with an orthographic projection of the metal material on the base substrate, to form a metal grid.

Structures in semiconductor devices, and methods for forming the structures, are described. In one embodiment, a hard mask layer of a deposition stack can be etched to pattern a hard mask. An interconnect layer of the deposition stack can be etched using the hard mask to pattern a plurality of metal lines. The hard mask can be removed. A liner layer of the deposition stack can be etched to remove a portion of the liner layer deposited directly on a dielectric layer of the deposition stack. In response to etching the liner layer, a remaining portion of the liner layer can be deposited between the metal lines and the dielectric layer.

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Processing methods described herein comprise forming a metal gate film on a narrow feature and a wide feature and depositing a hard mask on the metal gate film. The hard mask forms on the metal gate film at a top, bottom and sidewalls of the wide feature and on a top of the narrow feature to cover the metal gate film. Some processing methods comprise oxidizing the metal gate film on the narrow feature to convert a portion of the metal gate film to a metal oxide film. Some processing methods comprise etching the metal oxide film from the narrow feature to leave a gradient etch profile. Some processing methods comprise filling the narrow feature and the wide feature with a gap fill material comprising one or more of a metal nitride, titanium nitride (TiN) or titanium oxynitride (TiON), the gap fill material substantially free of seams and voids.

A semiconductor structure having metal contact features and a method for forming the same are provided. The method includes forming a dielectric layer covering an epitaxial structure over a semiconductor substrate and forming an opening in the dielectric layer to expose the epitaxial structure. The method includes forming a metal-containing layer over the dielectric layer and the epitaxial structure. The method includes heating the epitaxial structure and the metal-containing layer to transform a first portion of the metal-containing layer contacting the epitaxial structure into a metal-semiconductor compound layer. The method includes oxidizing the metal-containing layer to transform a second portion of the metal-containing layer over the metal-semiconductor compound layer into a metal oxide layer. The method includes applying a metal chloride-containing etching gas on the metal oxide layer to remove the metal oxide layer and forming a metal contact feature over the metal-semiconductor compound layer.

A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

A methodology for (a) the etching of films of Al.sub.2O.sub.3, HfO.sub.2, ZrO.sub.2, W, Mo, Co, Ru, SiN, or TiN, or (b) the deposition of tungsten onto the surface of a film chosen from Al.sub.2O.sub.3, HfO.sub.2, ZrO.sub.2, W, Mo, Co, Ru, Ir, SiN, TiN, TaN, WN, and SiO.sub.2, or (c) the selective deposition of tungsten onto metallic substrates, such as W, Mo, Co, Ru, Ir and Cu, but not metal nitrides or dielectric oxide films, which comprises exposing said films to WOCl.sub.4 in the presence of a reducing gas under process conditions.