An integrated circuit structure comprises a first and second vertical arrangement of horizontal nanowires in a PMOS region and in an NMOS region. A first gate stack having a P-type conductive layer surrounds the first vertical arrangement of horizontal nanowires. A second gate stack surrounds the second vertical arrangement of horizontal nanowires. In one embodiment, the second gate stack has an N-type conductive layer, the P-type conductive layer is over the second gate stack, and an N-type conductive fill is between N-type conductive layer and the P-type conductive layer to provide same polarity metal filled gates. In another embodiment, the second gate stack has an N-type conductive layer comprising Titanium (Ti) and “Nitrogen (N) having a low saturation thickness of 3-3.5 nm surrounding the nanowires, and the N-type conductive layer is covered by the P-type conductive layer.

A semiconductor device includes an active fin protruding from a substrate; a plurality of channel layers on the active fin and spaced apart from each other in a vertical direction; a gate pattern intersecting the active fin and the plurality of channel layers; and source/drain regions on recessed regions of the active fin on both sides of the gate pattern. The gate pattern includes a gate dielectric layer, inner conductive layers, and a conductive liner. The inner conductive layers are disposed between the plurality of channel layers, and between the active fin and a lowermost channel layer among the plurality of channel layers. The conductive liner has a first thickness on an upper surface of an uppermost channel layer in the vertical direction, and at least one of the inner conductive layers have a second thickness in the vertical direction. The first thickness is less than the second thickness.

A semiconductor device includes a base substrate including an NMOS region and a PMOS region. The PMOS region includes a first P-type region and a second P-type region. The semiconductor device also includes an interlayer dielectric layer, a gate structure formed through the interlayer dielectric layer and including an N-type region gate structure formed in the NMOS region, a first gate structure formed in the first P-type region and connected to the N-type region gate structure, and a second gate structure formed in the second P-type region and connected to the first gate structure. The direction from the N-type region gate structure to the second gate structure is an extending direction of the N-type region opening, and along a direction perpendicular to the extending direction of the N-type region opening, the width of the first gate structure is larger than the width of the second gate structure.

The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench defined by sidewalls of the substrate that surround the source region and the drain region. The one or more dielectric materials include one or more interior surfaces defining a recess within the one or more dielectric materials. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate material over the upper surface of the substrate and a second gate material. The second gate material completely fills the recess as viewed along a cross-sectional view.

The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

An IC includes a first and second active areas (AA) with a second conductivity type, a source and drain region, and an LDD extension to the source and drain in the first AA having a first conductivity type. A first bent-gate transistor includes a first gate electrode over the first AA extending over the corresponding LDD. The first gate electrode includes an angled portion that crosses the first AA at an angle of 45° to 80°. A second transistor includes a second gate electrode over the second AA extending over the corresponding LDD including a second gate electrode that can cross an edge of the second AA at an angle of about 90°. A first pocket distribution of the second conductivity type provides a pocket region under the first gate electrode. A threshold voltage of the first bent-gate transistor is ≥30 mV lower as compared to the second transistor.

A method of forming a semiconductor device is presented. A layer stack of alternating epitaxial materials including one or more layers is formed. The layer stack of alternating epitaxial materials into a first region of nano sheets and a second region of nano sheets is divided. A first field effect transistor on a working surface of a substrate using the nano sheets in the first region of nano sheets is formed. A stack of field effect transistors on the working surface of the substrate using the nano sheets in the second region of nano sheets is formed.

Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.

The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.