A silicon carbide device includes a silicon carbide body with a trench gate structure that extends from a first surface into the silicon carbide body. A body region is in contact with an active sidewall of the trench gate structure. A source region is in contact with the active sidewall and located between the body region and the first surface. The body region includes a first body portion directly below the source region and distant from the active sidewall. In at least one horizontal plane parallel to the first surface, a dopant concentration in the first body portion is at least 150% of a reference dopant concentration in the body region at the active sidewall and a horizontal extension of the first body portion is at least 20% of a total horizontal extension of the body region.

A semiconductor device includes a first electrode, a first semiconductor layer connected to the first electrode, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a fourth semiconductor layer on the third semiconductor layer, a second electrode connected to the third and fourth semiconductor layers, a gate electrode extending from the fourth toward the second semiconductor layer next to the third semiconductor layer, a field plate electrode extending in a direction from the fourth toward the second semiconductor layer next to the second semiconductor layer, and a first insulating film between the field plate electrode and the second semiconductor layer and having a lower end further from the field plate electrode than the first semiconductor layer; the first, second, and fourth semiconductor layers are of a first conductivity type; and the third semiconductor layer is of a second conductivity type.

A silicon carbide semiconductor device includes silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a trench, a gate insulating film, a gate electrode, and an interlayer insulating film. The first semiconductor layer and the second semiconductor layer constitute a first-conductivity-type semiconductor layer and in a deep region of the first-conductivity-type semiconductor layer at least 1 μm from an interface with the third semiconductor layer, a maximum value of a concentration of aluminum is less than 3.0×10.sup.13/cm.sup.3. In the deep region of the first-conductivity-type semiconductor layer, a maximum value of a concentration of boron is less than 1.0×10.sup.14/cm.sup.3.

A semiconductor device according to the present disclosure is an RC-IGBT in which an IGBT region 10 and a diode region 20 are provided adjacent to each other. The diode region 20 includes a p-type anode layer 25 provided on a first principal surface side of an n.sup.−-type drift layer 1, a p-type contact layer 24 provided on the first principal surface side of the p-type anode layer 25 and at a surface layer of a semiconductor substrate on the first principal surface side and connected with an emitter electrode 6, and an n.sup.+-type cathode layer 26 provided at a surface layer of the semiconductor substrate on a second principal surface side. The p-type contact layer 24 contains aluminum as p-type impurities, and the thickness of the p-type contact layer 24 is smaller than the thickness of an n.sup.+-type source layer 13 provided in the IGBT region 10.

A semiconductor device of an embodiment includes a first electrode; a second electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, and includes a first silicon carbide region of n-type; and a second silicon carbide region disposed between the first silicon carbide region and the first electrode, in contact with the first electrode, containing an at least one element selected from the group consisting of sulfur (S), selenium (Se), tellurium (Te), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), and tungsten (W), and containing at least one first atom of the at least one element, the first atom being bonded to four silicon atoms.

An SiC semiconductor device includes an SiC semiconductor layer of a first conductivity type having a main surface, a source trench formed in the main surface and having a side wall and a bottom wall, a source electrode embedded in the source trench and having a side wall contact portion in contact with a region of the side wall of the source trench at an opening side of the source trench, a body region of a second conductivity type formed in a region of a surface layer portion of the main surface along the source trench, and a source region of the first conductivity type electrically connected to the side wall contact portion of the source electrode in a surface layer portion of the body region.

A silicon carbide semiconductor device, including a semiconductor substrate, a first semiconductor layer provided on a first surface of the semiconductor substrate, a second semiconductor layer provided on a first surface of the first semiconductor layer, a third semiconductor layer provided on a first surface of the second semiconductor layer, a fourth semiconductor layer provided on a first surface of the third semiconductor layer, a plurality of first semiconductor regions of selectively provided in the fourth semiconductor layer at a first surface thereof, a gate electrode provided via a gate insulating film in the fourth semiconductor layer, between the first semiconductor regions and the third semiconductor layer, a first electrode provided on the first surface of the fourth semiconductor layer and surfaces of the first semiconductor regions, and a second electrode provided on a second surface of the semiconductor substrate. Protons are introduced into the second semiconductor layer and have a concentration of 1.0×10.sup.13/cm.sup.3 to 1.0×10.sup.14/cm.sup.3.

A semiconductor substrate is fabricated in which only first and second n.sup.−-type epitaxial layers are stacked on an n.sup.+-type starting substrate, a front surface of the semiconductor substrate being a continuously flat surface from an active region to a chip end. In an edge termination region, as a voltage withstanding structure, a ring-shape FLR is provided in which p-type FLR regions concentrically surrounding a periphery of the active region are disposed apart from one another. The p-type FLR regions each have a layered structure configured by multiple p-type regions (partial FLRs) that are adjacent to one another in a depth direction and formed by performing ion implantation of a p-type impurity for each epitaxial growth of the first and the second n.sup.−-type epitaxial layers configuring the semiconductor substrate. A predetermined breakdown voltage is obtained by adjusting the number of stacked layers and impurity concentrations of the partial FLRs of the p-type FLR regions.

A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, first base regions of a second conductivity type, second base regions of the second conductivity type, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an interlayer insulating film, first electrodes, a second electrode, and trenches. Between adjacent first base regions, at least two of the trenches, at least two of the gate electrodes, and at least two of the second base regions are disposed, the second base regions disposed between the adjacent first base regions being disposed separate from one another and separate from the first base regions, in a direction in which the trenches are arranged.

A main semiconductor device element is SiC-MOSFETs with a trench gate structure, the main semiconductor device element having main MOS regions responsible for driving the MOSFETs and main SBD regions that are regions responsible for SBD operation. The main MOS regions and the main SBD regions are adjacent to one another and each pair of a main MOS region and a main SBD region adjacent thereto share one trench. In the main SBD regions, first and second p-type regions, and Schottky electrodes at the front surface of the semiconductor substrate and forming Schottky junctions with an n.sup.−-type drift region are provided. The first p-type regions are provided along sidewalls of the trenches, in contact with the first p.sup.+-type regions at the bottoms of the trenches. The second p-type regions are provided between the first p-type regions and the Schottky electrodes, and are electrically connected to these regions.