A silicon carbide power MOSFET with enhanced body diode applying a repetitive polygonal or circular layout design on a first surface, having: a substrate; an N-type SiC region with a first doping concentration formed on the substrate; a JFET region or a trench insulating gate region formed inside the N-type SiC region; a metal layer formed on the N-type SiC region; a P-type SiC region with a second doping concentration or a Schottky region, wherein the P-type SiC region is formed on one side of the JFET region or one side of the trench insulating gate region, the P-type SiC region and the metal layer are contacted directly forming an ohmic contact, the Schottky region and the metal layer are contacted directly forming a Schottky contact; and a conventional source region on another side of the JFET region.

In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.

A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.

The present disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage and the clamping diode defines a second breakdown voltage, with the first breakdown voltage being greater than the second breakdown voltage so that the clamp diode is configured and arranged to receive a low avalanche current and the MOSFET is configured and arranged to receive a high avalanche current.

An object of the present invention is to provide a highly reliable semiconductor device by preventing precipitation of an oxide to prevent peeling of a resin layer. The semiconductor device includes: a resin layer provided so that at least a part of the resin layer extends on a front surface of a semiconductor layer on an outer peripheral side with respect to an outer peripheral end of a field insulating film; and a floating well region spaced apart from a termination well region in a surface layer of the semiconductor layer, the floating well region formed to be in contact with an outer peripheral end of the field insulating film to extend to the outer peripheral side with respect to the outer peripheral end of the field insulating film.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer portion of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.

A semiconductor device includes a semiconductor substrate, and the semiconductor substrate is divided into an IGBT region, a diode region, and a MOSFET region. A drift layer of n.sup.−-type is provided in the semiconductor substrate. The drift layer is shared among the IGBT region, the diode region, and the MOSFET region. In the semiconductor substrate, the diode region is always disposed between the IGBT region and the MOSFET region to cause the IGBT region and the MOSFET region to be separated from each other without being adjacent to each other.

A semiconductor device is proposed. A trench gate structure extends from a first surface into a silicon carbide semiconductor body along a vertical direction. A trench contact structure extends from the first surface into the silicon carbide semiconductor body along the vertical direction. A source region of a first conductivity type and a body region of a second conductivity type adjoin a first sidewall of the trench gate structure. A diode region of the second conductivity type adjoins a second sidewall of the trench gate structure opposite to the first sidewall. A shielding region of the second conductivity type adjoins a bottom of the trench contact structure, the shielding region being arranged at a lateral distance to the trench gate structure.

A semiconductor device has first second-conductivity-type high-concentration regions, second second-conductivity-type high-concentration regions, third second-conductivity-type high-concentration regions, and fourth second-conductivity-type high-concentration regions. The first connecting regions each connect a portion of each of the first second-conductivity-type high-concentration regions and a portion of each of the second second-conductivity-type high-concentration regions. The second connecting regions each connect a portion of each of the third second-conductivity-type high-concentration regions and a portion of each of the fourth second-conductivity-type high-concentration regions. A ratio of a mathematical area of the first connecting regions to a mathematical area of the second second-conductivity-type high-concentration regions is greater than a ratio of a mathematical area of the second connecting regions to a mathematical area of the fourth second-conductivity-type high-concentration regions.