A semiconductor device having a semiconductor substrate that includes a first-conductivity-type substrate and a first-conductivity-type epitaxial layer, and a plurality of trenches reaching a predetermined depth from a main surface of the semiconductor substrate to terminate in the first-conductivity-type epitaxial layer. The semiconductor substrate includes a hydrogen-donor introduced part, of which a concentration of a hydrogen donor is greatest at a depth position that is separate from bottoms of the trenches by a distance at least two times of the depth of the trenches. The impurity concentration of an impurity dopant of the first-conductivity-type substrate being lower than that of the first-conductivity-type epitaxial layer. A difference between a first resistivity, corresponding to a total impurity concentration of the impurity dopant and the hydrogen donor of the first-conductivity-type substrate, and a second resistivity, corresponding to the impurity concentration of the impurity dopant of the first-conductivity-type epitaxial layer, is at most 20%.

A gate drive circuit has a capacitor and a gate drive voltage source connected in series with a gate terminal of a voltage-driven switching device. The gate drive source voltage feeds, as a gate drive voltage, a voltage higher than the sum of the voltage applied to a gate-source parasitic capacitance of the switching device when the switching device is in a steady ON state and the voltage applied to, of any circuit component interposed between the gate drive voltage source and the gate terminal of the switching device, a circuit component other than the capacitor (such as an upper transistor forming the output stage of the driver). No other circuit component (such as a resistor connected in parallel with the capacitor) is essential but the capacitor as the sole circuit component to be directly connected to the gate terminal of the switching device.

A wide gap semiconductor device has: a drift layer 12 using a first conductivity type wide gap semiconductor material; a well region 20, being a second conductivity type and provided in the drift layer 12; a polysilicon layer 150 provided on the well region 20; an interlayer insulating film 65 provided on the polysilicon layer 150; a gate pad 120 provided on the interlayer insulating film 65; and a source pad 110 electrically connected to the polysilicon layer 150.

A crystal cutting method includes a step of preparing a crystal structure body constituted of a hexagonal crystal, a first cutting step of cutting the crystal structure body along a [1-100] direction of the hexagonal crystal and forming a first cut portion in the crystal structure body and a second cutting step of cutting the crystal structure body along a [11-20] direction of the hexagonal crystal and forming a second cut portion crossing the first cut portion in the crystal structure body.

Provided are: injection control regions of a second conductivity type provided on a charge transport region of a first conductivity type; main electrode regions of the first conductivity type provided on the injection control regions; insulated gate electrode structures going through the main electrode region and the injection control regions in the depth direction; an injection suppression region going through the main electrode regions and the injection control regions in the depth direction so as to form a pn junction in a path leading to the charge transport region, the injection suppression region including a semiconductor material with a narrower bandgap than a material of the charge transport region; and a contact protection region of the second conductivity type contacting the bottom surface of the injection suppression region.

A semiconductor component includes a field effect transistor structure in a SiC semiconductor body having a gate structure at a first surface of the SiC semiconductor body and a drift zone of a first conductivity type. A zone of the first conductivity type is formed in a vertical direction between a semiconductor region of a second conductivity type and the drift zone. The zone is spaced apart from the gate structure and is at a maximal distance of 1 m from the semiconductor region in the vertical direction.

A system for monitoring a junction temperature of a semiconductor device includes a sensing resistor electrically coupled to a source terminal of the semiconductor device in a gate loop of the semiconductor device. The system includes a detection circuit electrically coupled to the gate loop of the semiconductor device and configured to measure a voltage difference across the sensing resistor. The system also includes an electronic control unit electrically coupled to the gate loop and the detection circuit. The electronic control unit is configured to determine a first gate current peak during a switching process of the semiconductor device, wherein the first gate current peak is determined based on the voltage detected by the detection circuit. The electronic control unit is configured to determine the junction temperature based on the first gate current peak.

A power electronic arrangement includes a semiconductor switch structure configured to assume a forward conducting state. A steady-state current carrying capability of the semiconductor switch structure in the forward conducting state is characterized by a nominal current. The semiconductor switch structure is configured to conduct, in the forward conducting state, at least a part of a forward current in a forward current mode of the power electronic arrangement. A diode structure electrically connected in antiparallel to the semiconductor switch structure is configured to conduct at least a part of a reverse current in a reverse mode of the power electronic arrangement. A thyristor structure electrically connected in antiparallel to the semiconductor switch structure has a forward breakover voltage lower than a diode on-state voltage of the diode structure at a critical diode current value, the critical diode current value amounting to at most five times the nominal current.

A semiconductor device according to an embodiment includes first electrode; second electrode; silicon carbide layer between the first electrode and the second electrode, the silicon carbide layer having first and second plane, the silicon carbide layer including first silicon carbide region of first-conductivity-type, second silicon carbide region and third silicon carbide region between the first silicon carbide region and the first plane, fourth silicon carbide region between the second silicon carbide region and the first plane, the fourth silicon carbide region contacting the first electrode, fifth silicon carbide region between the second silicon carbide region and the third silicon carbide region, the fifth silicon carbide region having a higher first-conductivity-type impurity concentration than the first silicon carbide region, sixth silicon carbide region between the fifth silicon carbide region and the first plane, the sixth silicon carbide region contacting the first electrode; gate electrode facing the second silicon carbide region.

A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source regions of the current sense transistor. The doped resistor region has an opposite conductivity type as the source regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.