A semiconductor device includes a vertical transistor and a body diode. Various improvements to the semiconductor device allow for improved performance of the body diode, in particular to reduced snappiness and increased softness.

A wide gap semiconductor device has: a drift layer 12 using a first conductivity type wide gap semiconductor material; a well region 20, being a second conductivity type and provided in the drift layer 12; a polysilicon layer 150 provided on the well region 20; an interlayer insulating film 65 provided on the polysilicon layer 150; a gate pad 120 provided on the interlayer insulating film 65; and a source pad 110 electrically connected to the polysilicon layer 150.

A semiconductor component includes a semiconductor component, including: a merged PiN Schottky (MPS) diode structure in a SiC semiconductor body having a drift zone of a first conductivity type; an injection region of a second conductivity type adjoining a first surface of the SiC semiconductor body; a contact structure at the first surface, the contact structure forming a Schottky contact with the drift zone and electrically contacting the injection region; and a zone of the first conductivity type formed between the injection region and a second surface of the SiC semiconductor body, the second surface being situated opposite the first surface. The zone is at a maximal distance of 1 μm from the injection region of the second conductivity type.

A silicon carbide semiconductor device, including a semiconductor substrate, a first semiconductor layer provided on a first surface of the semiconductor substrate, a second semiconductor layer provided on a first surface of the first semiconductor layer, a third semiconductor layer provided on a first surface of the second semiconductor layer, a fourth semiconductor layer provided on a first surface of the third semiconductor layer, a plurality of first semiconductor regions of selectively provided in the fourth semiconductor layer at a first surface thereof, a gate electrode provided via a gate insulating film in the fourth semiconductor layer, between the first semiconductor regions and the third semiconductor layer, a first electrode provided on the first surface of the fourth semiconductor layer and surfaces of the first semiconductor regions, and a second electrode provided on a second surface of the semiconductor substrate. Protons are introduced into the second semiconductor layer and have a concentration of 1.0×10.sup.13/cm.sup.3 to 1.0×10.sup.14/cm.sup.3.

According to an aspect of the present disclosure, a semiconductor device includes a FWD region that has, on an upper surface side of a substrate, a p-type anode region, a first p-type contact region having a higher p-type impurity concentration than the p-type anode region, and a first trench, and an IGBT region that surrounds the FWD region in plan view via a boundary region, and has an n-type emitter region, a second p-type contact region, and a second trench on the upper surface side of the substrate, wherein the first trench is formed annularly along an outer edge of the FWD region in plan view, the second trench is formed annularly along an outer edge of the boundary region in plan view, and only a p-type region is provided on an upper surface side of the boundary region.

A power semiconductor device including an epitaxial layer and a fabrication method thereof are provided. A first well region and a second well region separated from each other respectively extend from a surface of the epitaxial layer into the epitaxial layer. A floating doped region is located in the epitaxial layer and between the first well region and the second well region. The floating doped region is separated from the first well region and the second well region. A first doped region and a second doped region respectively extend from the surface of the epitaxial layer into the first well region and the second well region. A gate structure is located on the epitaxial layer and is adjacent to the first doped region and the second doped region. The gate structure is at least partially overlapped with the floating doped region.

An embodiment of a semiconductor device comprises a SiC semiconductor body, a gate dielectric and a gate electrode. A first trench extends from a first surface of the SiC semiconductor body into the SiC semiconductor body. A junction material is in the first trench, wherein the junction material and the SiC semiconductor body form a diode.

A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, first base regions of a second conductivity type, second base regions of the second conductivity type, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an interlayer insulating film, first electrodes, a second electrode, and trenches. Between adjacent first base regions, at least two of the trenches, at least two of the gate electrodes, and at least two of the second base regions are disposed, the second base regions disposed between the adjacent first base regions being disposed separate from one another and separate from the first base regions, in a direction in which the trenches are arranged.

A semiconductor device includes: a first semiconductor chip including a first MOSFET of n-type and a first parasitic diode; and a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode. A first source electrode and a first gate wiring are formed in a first front surface of the first semiconductor chip, and a first drain electrode is formed in a first back surface of the first semiconductor chip. A second source electrode and a second gate wiring are formed in a second front surface of the second semiconductor chip, and a second drain electrode is formed in a second back surface of the second semiconductor chip. The first front surface and the second front surface face each other such that the first source electrode and the second source electrode are in contact with each other via a conductive paste.

A semiconductor device of embodiments includes a first gate electrode, a second gate electrode, a third gate electrode extending in a first direction, and a gate wiring line extending in a second direction crossing the first direction and to which the first to the third gate electrodes are connected. Assuming distance between the first and the second gate electrode in the second direction in a first region is S1, distance between the first and the second gate electrode in the second direction in a second region closer to the gate wiring line than the first region is S2, distance between the second and the third gate electrode in the second direction in the first region is S3, and distance between the second and the third gate electrode in the second direction in the second region is S4, following Expressions are satisfied,
S1<S3, S1<S2, S3>S4.