A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor including a breakdown voltage clamp includes a drain n+ region, a source n+ region, a gate, and a p-type reduced surface field (PRSF) layer including one or more bridge portions. Each of the one or more bridge portions extends below the drain n+ region in a thickness direction. Another LDMOS transistor includes a drain n+ region, a source n+ region, a gate, an n-type reduced surface field (NRSF) layer disposed between the source n+ region and the drain n+ region in a lateral direction, a PRSF layer disposed below the NRSF layer in a thickness direction orthogonal to the lateral direction, and a p-type buried layer (PBL) disposed below the PRSF layer in the thickness direction. The drain n+ region is disposed over the PBL in the thickness direction.

A wide gap semiconductor device has: a first MOSFET region (M0) having a first gate electrode 10 and a first source region 30 provided in a first well region 20 made of a second conductivity type; a second MOSFET region (M1) provided below a gate pad 100 and having a second gate electrode 110 and a second source region 130 provided in a second well region 120 made of the second conductivity type; and a built-in diode region electrically connected to the second gate electrode 110. The second source region 130 of the second MOSFET region (M1) is electrically connected to the gate pad 100.

In a semiconductor device using, as a FWD, a diode formed in a silicon carbide (SiC) substrate, while preventing gate oscillation, an increase of switching loss is suppressed at the time of a temperature increase also. A semiconductor device includes: a transistor element; a diode element formed in a SiC substrate; and a resistive element that is electrically connected to a gate of the transistor element, and has a resistor temperature coefficient which is within the range of ±150×10.sup.−6/K. The resistive element has a resistor formed of a ceramic-containing material.

A method for improving breakdown voltage of a Laterally Diffused Metal Oxide Semiconductor (LDMOS) includes biasing a first well of a Field Effect Transistor (FET) to a first voltage. The first well is laterally separated from a second well. An isolation ring is charged to a second voltage in response to the first voltage exceeding a breakdown voltage of a diode connected between the isolation ring and the first well. The isolation ring laterally surrounds the FET and contacts a buried layer (BL) extending below the first well and the second well. A substrate is biased to a third voltage being less than or equal to the first voltage. The substrate laterally extends below the BL and contacts the BL.

A semiconductor device, a terminal device, and a manufacturing method, where the device uses a groove-gate structure and a double-longitudinal reduced surface field (RESURF) technology using a longitudinal field plate and a longitudinal PN junction, and a channel is disposed on a bottom of a groove. The device is implemented based on a conventional spit trench gate metal-oxide-semiconductor (MOS) process or a monolithic integrated bipolar-complementary MOS (CMOS)-double-diffused MOS field-effect transistor (DMOS) (BCD) process technology.

A motor drive device includes a single-phase inverter which is an inverter including a plurality of switching elements. The inverter converts a direct-current voltage output from a direct-current power supply into an alternating-current voltage, by operation of the plurality of switching elements operating, and applies the alternating-current voltage to a motor. The motor drive device includes a control power supply outputting power having a voltage lower than the direct-current voltage, by using the direct-current voltage. The motor drive device includes a drive signal generation unit driven by the power. The drive signal generation unit generates drive signals driving the plurality of switching elements, and outputs the generated drive signals to the plurality of switching elements. The motor drive device includes a power supply switch operating so as to allow supply of the power from the control power supply to the drive signal generation unit when a rotation speed of the motor is higher than a threshold. The power supply switch operates so as to stop the supply of the power from the control power supply to the drive signal generation unit when the rotation speed is lower than the threshold.

An apparatus comprises a Laterally Diffused Metal Oxide Semiconductor (LDMOS) comprising a drain connectable to a drift region and a source connectable to a body region. A diode comprises a cathode electrically coupled to the drift region, wherein during an operating condition, the anode is charged to a bias voltage less than a high voltage applied to the drain and greater than a low voltage applied to the source. The anode is laterally displaced from the drain by a first distance. A first deep trench isolation (DTI) is proximate to the source and disposed to laterally surround the LDMOS. A shield junction is proximate to the first DTI and on an opposite side of the source, and electrically connected to the anode.

A rectifier includes a first transistor of a drain/source common field effect type and a second transistor of a drain/source common field effect type in which the second transistor is diode-connected to the first transistor so as to allow the first transistor to perform a diode operation, and configures a rectifier stage with the first transistor.

A wide gap semiconductor device has: a first MOSFET region (M0) having a first gate electrode 10 and a first source region 30 provided in a first well region 20 made of a second conductivity type; a second MOSFET region (M1) provided below a gate pad 100 and having a second gate electrode 110 and a second source region 130 provided in a second well region 120 made of the second conductivity type; and a built-in diode region electrically connected to the second gate electrode 110. The second source region 130 of the second MOSFET region (M1) is electrically connected to the gate pad 100.

A semiconductor integrated circuit includes: a p.sup.-type semiconductor substrate defining a high-potential side circuit area and a low-potential side circuit area separated from each other; a high-side n well provided in an upper part of the semiconductor substrate in the high-potential side circuit area; a high-side p well provided in the high-side n well; and a p-type semiconductor region provided in an upper part of the semiconductor substrate in the low-potential side circuit area; and n.sup.+-type semiconductor region provided to be brought contact with the p-type semiconductor region, wherein a whole n-type semiconductor region including the n.sup.+-type semiconductor region, has an impurity concentration higher than an impurity concentration of the high-side n well.