A transistor arrangement includes: a layer stack with first and second semiconductor layers of complementary first and second doping types; a first source region of a first transistor device adjoining the first semiconductor layers; a first drain region of the first transistor device adjoining the second semiconductor layers and spaced apart from the first source region; gate regions of the first transistor device, each gate region adjoining at least one second semiconductor layer, being arranged between the first source region and the first drain region, and being spaced apart from the first source region and the first drain region; a third semiconductor layer adjoining the layer stack and each of the first source region, first drain region, and each gate region; and active regions of a second transistor device integrated in the third semiconductor layer in a second region spaced apart from a first region of the third semiconductor layer.

A lateral junction diode device includes a substrate having at least a semiconductor surface layer. A depletion-mode LDMOS device is in the semiconductor surface layer including a source, drain, and a gate above a gate dielectric, and a channel region under the gate on the gate dielectric. A drift region is between the channel region and the drain, wherein the drain also provides a cathode for the lateral junction diode device. An embedded diode includes a second cathode and an anode that is shared with the device. The embedded diode is junction isolated by an isolation region located between the anode and the source. The anode and isolation region are directly connected to the gate and the second cathode is directly connected to the source.

A semiconductor integrated circuit includes: a p.sup.-type semiconductor substrate defining a high-potential side circuit area and a low-potential side circuit area separated from each other; a high-side n well provided in an upper part of the semiconductor substrate in the high-potential side circuit area; a high-side p well provided in the high-side n well; and a p-type semiconductor region provided in an upper part of the semiconductor substrate in the low-potential side circuit area; and n.sup.+-type semiconductor region provided to be brought contact with the p-type semiconductor region, wherein a whole n-type semiconductor region including the n.sup.+-type semiconductor region, has an impurity concentration higher than an impurity concentration of the high-side n well.

A motor drive device includes a single-phase inverter that converts a direct-current voltage into an alternating-current voltage applied to a motor. The motor drive device includes a control power supply outputting power having a voltage lower than the direct-current voltage. The motor drive device includes a drive signal generation unit driven by the power. The drive signal generation unit generates drive signals driving switching elements of the inverter. The motor drive device includes a power supply switch operating so as to allow supply of the power from the control power supply to the drive signal generation unit when a rotation speed of the motor is higher than a threshold. The power supply switch operates so as to stop the supply of the power from the control power supply to the drive signal generation unit when the rotation speed is lower than the threshold.

A transistor assembly with gate current shunting capability includes first field effect transistor (FET), a first pull-up current source, a first pull-down current source, a first switching device, a control circuit, a capacitor, and a second FET. The first FET is an N-channel FET including a first gate, a first drain, and a first source. The first drain is electrically coupled to a first power supply. Each of the pull-up current source and the pull-down current source is electrically coupled to the first gate. The first switching device is electrically coupled in series with the first pull-down current source and is controlled by a first control signal. The control circuit is at least partially powered by a second power supply and generates the first control signal.

The capacitor and the second FET collectively shunt current away from the first gate during a pre-power operating state of the transistor assembly.

To provide a high-withstand-voltage lateral semiconductor device in which ON-resistance or drain current density is uniform at an end portion and a center portion of the device in a gate width direction. A lateral N-type MOS transistor 11 formed on an SOI substrate includes a trench isolation structure 10b filled with an insulating film at an end portion of the transistor. An anode region 6 of a diode 12 is provided adjacent to a P-type body region 1 of the transistor through the trench isolation structure 10b and a cathode region 15 of the diode 12 is also provided adjacent to an N-type drain-drift region 4 of the transistor through the trench isolation structure 10b so as to cause electric field to be applied to the trench isolation structure 10b to be zero when a voltage is applied across the transistor.

An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a doped region formed in the source region. The source region and the drain region include a first conductivity type, and the doped region includes a second conductivity type complementary to the first conductivity type. The doped region is electrically connected to a ground potential.

To provide a semiconductor apparatus including: a semiconductor substrate having a drift region; an emitter region provided inside the semiconductor substrate and above the drift region; a base region provided between the emitter and drift regions; an accumulation region provided between the base and drift regions; and a plurality of gate trench portions provided to penetrate the accumulation region from an upper surface of the semiconductor substrate. The base region has: a low concentration base region provided in contact with the gate trench portions; and a high concentration base region provided apart from the gate trench portions and having a doping concentration higher than the low concentration base region. The high concentration base region is provided below the emitter region, and a width of the high concentration base region in a depth direction of the semiconductor substrate is larger than 0.1 m.

A semiconductor device includes: a first-conductivity-type drift layer including a first-conductivity-type impurity, vacancy-oxygen-hydrogen complex defects each caused by a vacancy, an oxygen atom, and a hydrogen atom, divacancy-and-vacancy-phosphorus complex defects, having a trap density level lower than a trap density level of the vacancy-oxygen-hydrogen complex defect, and third complex defects; a plurality of donor layers provided at different depths in a depth direction of the first-conductivity-type drift layer, wherein each of the plurality of donor layers includes donors caused by the vacancy-oxygen-hydrogen complex defects, and each of the plurality of donor layers has an impurity concentration distribution that includes a first portion with a maximum impurity concentration and a second portion with a concentration gradient in which the impurity concentration is reduced from the first portion to both main surfaces of the first-conductivity-type drift layer; and a second-conductivity-type semiconductor region provided on one main surface of the first-conductivity-type drift layer.

A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.