Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/02
Bonding areas; Manufacturing methods related thereto
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H01L2224/04
Structure, shape, material or disposition of the bonding areas prior to the connecting process
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H01L2224/05
of an individual bonding area
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H01L2224/05198
with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
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H01L2224/05493
with a principal constituent of the material being a solid not provided for in groups H01L2224/054 - H01L2224/05491, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
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H01L2224/05493

Semiconductor Device and Method of Making a Dual-Side Molded System-in-Package with Fine-Pitched Interconnects
20240379480 · 2024-11-14 · ·

A semiconductor device has a substrate. An electrical component is disposed over a first surface of the substrate. A solder paste is disposed over the first surface of the substrate. A conductive pillar is disposed on the solder paste. An encapsulant is deposited over the first surface of the substrate, the electrical component, and the conductive pillar. A solder bump is formed over the conductive pillar.