Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/02
Bonding areas; Manufacturing methods related thereto
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H01L2224/04
Structure, shape, material or disposition of the bonding areas prior to the connecting process
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H01L2224/05
of an individual bonding area
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H01L2224/05698
with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
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H01L2224/0599
with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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H01L2224/0599

DIE WITH CONNECTION PAD
20250140745 · 2025-05-01 ·

An IC (integrated circuit) package include an interconnect having a die attach pad and lead. The IC package also includes a die with a first side mounted on the die attach pad and a second side opposing the first side. The second side having a planar region. The planar region having selective polyimide structures between contact points of a connection pad. The IC package also includes a clip coupled to the connection pad and to a lead of the leads.