A method for executing a direct transfer of semiconductor device die from a first substrate to transfer locations on a second substrate. The method includes determining a position of impact wires disposed on a transfer head, semiconductor device die, and transfer locations; determining whether there are at least two positions that an impact wire, a semiconductor device die, and a transfer locations are aligned within a threshold tolerance; and transferring, by the impact wires, the semiconductor device die such that the semiconductor device die detaches from the first substrate and attaches to transfer locations on the second substrate. The transferring being completed based at least in part on determining that the impact wire, the semiconductor device die, and the circuit trace are aligned within the threshold tolerance.

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

A multi-grooved interposer includes an interposer substrate containing multiple parallel grooves laterally extending along a first direction and laterally spaced among one another along a second direction, and multiple conductive strips. The multiple parallel grooves are recessed from front side surfaces of the multi-grooved interposer in a third direction toward a back side surface of the multi-grooved interposer. The multiple conductive strips continuously extend across recessed surfaces in the multiple parallel grooves and the front side surfaces along the second direction with an undulating surface profile to provide electrically conductive paths across the multiple parallel grooves. Each of the multiple parallel grooves is configured to receive an edge of a respective semiconductor chip.

A method of removing a substrate, comprising: forming a growth restrict mask with a plurality of striped opening areas directly or indirectly upon a GaN-based substrate; and growing a plurality of semiconductor layers upon the GaN-based substrate using the growth restrict mask, such that the growth extends in a direction parallel to the striped opening areas of the growth restrict mask, and growth is stopped before the semiconductor layers coalesce, thereby resulting in island-like semiconductor layers. A device is processed for each of the island-like semiconductor layers. Etching is performed until at least a part of the growth restrict mask is exposed. The devices are then bonded to a support substrate. The GaN-based substrate is removed from the devices by a wet etching technique that at least partially dissolves the growth restrict mask. The GaN substrate that is removed then can be recycled.

Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.

A method of making a micro-module structure comprises providing a substrate, the substrate having a substrate surface and comprising a substrate post protruding from the substrate surface. A component is disposed on the substrate post, the component having a component top side and a component bottom side opposite the component top side, the component bottom side disposed on the substrate post. The component extends over at least one edge of the substrate post. One or more component electrodes are disposed on the component.

Various embodiments include a semiconductor component comprising: a first carrier part; a second carrier part arranged opposite the first carrier part; a semiconductor element arranged between the first carrier part and the second carrier part; a contact surface arranged on one of the parts; a contact sleeve arranged on one of the carrier parts opposite the contact surface; and a contact pin with, at one axial end, an end face providing an electrical contact connection of the contact surface and, in a region averted from said axial end, a connection region for the connection of the contact pin with the contact sleeve by means of press fitting. At least one of the first carrier part or the second carrier part comprises a printed conductor connected to the contact surface and/or to the contact sleeve.

A semiconductor package may include: a substrate; an upper chip disposed on the substrate; a first lower semiconductor chip disposed between the substrate and the upper chip, and electrically connected to the substrate; a second lower semiconductor chip disposed between the substrate and the upper chip, and electrically connected to the substrate; and an interposer chip disposed between the substrate and the upper chip, wherein the interposer chip includes a through-via electrically connecting the upper chip to the substrate, wherein the first lower semiconductor chip is electrically connected to the upper chip, wherein a lower surface of the upper chip is disposed on an upper surface of the first lower semiconductor chip, and wherein the second lower semiconductor chip is electrically connected to the upper chip, wherein a lower surface of the upper chip is disposed on an upper surface of the second lower semiconductor chip.

A connection structural body includes a first connection terminal, a second connection terminal facing the first connection terminal, and a bonding member bonding the first connection terminal and the second connection terminal. The bonding member includes an intermetallic compound layer that is formed by a roughened-surface metal film, structured by deposits of metal piled over one another such that a large number of pores are formed, and a solder layer that is disposed in the pores.