Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/02
Bonding areas; Manufacturing methods related thereto
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H01L2224/07
Structure, shape, material or disposition of the bonding areas after the connecting process
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H01L2224/08
of an individual bonding area
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H01L2224/0812
the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
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H01L2224/08151
the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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H01L2224/08221
the body and the item being stacked
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H01L2224/08253
the bonding area connecting to a potential ring of the item
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H01L2224/08253

SEALING RING, STACKED STRUCTURE, AND METHOD FOR MANUFACTURING SEALING RING
20230140743 · 2023-05-04 ·

Embodiments of the disclosure provide a sealing ring, a stacked structure, and a method for manufacturing a sealing ring. The sealing ring is arranged at a periphery of a device area of a chip, and includes an inner ring structure, a middle ring structure, and an outer ring structure. The middle ring structure is connected to the device area through a doped well. The doped well is located in part of a substrate corresponding to the inner ring structure and the middle ring structure, and is isolated from the inner ring structure.

Sealing ring, stacked structure, and method for manufacturing sealing ring
12417952 · 2025-09-16 · ·

Embodiments of the disclosure provide a sealing ring, a stacked structure, and a method for manufacturing a sealing ring. The sealing ring is arranged at a periphery of a device area of a chip, and includes an inner ring structure, a middle ring structure, and an outer ring structure. The middle ring structure is connected to the device area through a doped well. The doped well is located in part of a substrate corresponding to the inner ring structure and the middle ring structure, and is isolated from the inner ring structure.