In semiconductor device, a substrate unit includes an insulating substrate, a first conductor substrate and a second conductor substrate which are disposed on one main surface of the insulating substrate and spaced apart from each other, and a third conductor substrate which is disposed on the other main surface opposite to the one main surface of the insulating substrate. A terminal is connected to a surface of a semiconductor element opposite to the first conductor substrate. The terminal extends from a region above the semiconductor element to a region above the second conductor substrate while being connected to the second conductor substrate. At least a part of the terminal, the substrate unit and the semiconductor element is sealed by a resin. The third conductor substrate is exposed from the resin.

A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The semiconductor chip is disposed on a first substrate electrode, and one end of a Cu wire is bonded onto the Ag fired cap by means of an ultrasonic wave. There is provided a semiconductor device capable of improving a power cycle capability, and a fabrication method of such a semiconductor device.

Provided is an integrated electric power steering apparatus including a positive-side wiring pattern configured to connect a positive side of a power supply and a positive side of an inverter circuit and a negative-side wiring pattern configured to connect a negative side of the power supply and a negative side of the inverter circuit, in which one of the wiring patterns is formed on a central side of a wiring board and another of the wiring patterns is formed on an outer periphery side of the wiring board. A plurality of switching elements forming the inverter circuit are mounted between the positive-side wiring pattern and the negative-side wiring pattern formed on the wiring board.

A semiconductor device includes: an upper-surface electrode on an upper surface of a semiconductor element; a plated layer on an upper surface of the upper-surface electrode; gate runners penetrating the plated layer and formed to extend above the upper surface of the semiconductor element; and a metal connecting plate arranged above the plated layer and electrically connected to the upper-surface electrode, wherein the metal connecting plate has a joint portion parallel to the upper surface of the semiconductor element and has a rising portion at an end of the joint portion, the rising portion extending in a direction away from the semiconductor element, and in a plane parallel to the upper surface of the semiconductor element, a first distance, which is a shortest distance between the rising portion and the gate runner not intersecting the rising portion, is equal to or longer than 1 mm.

The present invention relates to a metal clip structure and a semiconductor package including the same, and more particularly, to a metal clip structure and a semiconductor package including the same which may be light-weighted, increase bond strength of a conductive wire, and minimize contamination occurring due to a solder material used to bond a semiconductor chip to a metal pad.

In a power semiconductor module, the 0.2% yield strength of solder under a lead terminal that bonds the lead terminal and a semiconductor element is set to be lower than the 0.2% yield strength of solder under the semiconductor element that bonds the semiconductor element and an insulating substrate. As a result, the lead terminal is expanded with self-heating by energization of the semiconductor element, and stress is applied to the semiconductor element via the solder under the lead terminal. However, the solder under the lead terminal with low 0.2% yield strength reduces the stress that is applied to the semiconductor element. Thus, the reliability of a surface electrode of the semiconductor element that is bonded to the solder under the lead terminal is improved.

A semiconductor module, including: a circuit board including a semiconductor element; a lead bonded to an electrode of the semiconductor element by a bonding material; and a sealing material sealing the semiconductor element and the lead. The lead includes: a bonding portion bonded to the electrode, and a roughening recess formed on an upper surface of the bonding portion. The roughening recess includes: a main recess having a first wall surfaces and a second wall surface opposite to each other, and a barbed portion formed on the first wall surface and protruding toward the second wall surface, and a sub-recess having: a center, which is located, in a plan view of the semiconductor module, outside the main recess and at a position away from the first wall surface by a predetermined distance, and an inclined surface that becomes shallower from the center toward an opening end of the main recess.

Disclosed is a power semiconductor package including a power transistor having a first power electrode and a gate electrode on its top surface and a second power electrode on its bottom surface. The second power electrode is configured for attachment to a partially etched leadframe segment, where the partially etched leadframe segment is attached to a substrate. A conductive clip is situated over the first power electrode and extends to the substrate in order to couple the first power electrode to the substrate without using a leadframe.

In a power semiconductor device, an IGBT has a collector electrode bonded to a metal plate by a bonding material. A diode has a cathode electrode bonded to the metal plate by the bonding material. An interconnection member is bonded to an emitter electrode of the IGBT by a bonding material. The bonding material includes a bonding material and a bonding material. The bonding material is interposed between the IGBT and the interconnection member. The bonding material fills a through hole formed in the interconnection member. The bonding material reaches the bonding material and is therefore connected to the bonding material.

A semiconductor module, including: a stacked substrate, which includes an insulating plate, and a plurality of circuit boards formed on an upper surface of the insulating plate; a semiconductor element formed on an upper surface of one of the plurality of circuit boards; and a metal wiring board formed on an upper surface of the semiconductor element. The metal wiring board has a plate-shaped bonding portion bonded to the upper surface of the semiconductor element via a bonding material. The plate-shaped bonding portion has a plurality of recessed portions formed on an upper surface thereof, each recessed portion is of a hexagonal shape in a plan view of the semiconductor module.