A structure of a printed circuit board and a carrier is coupled with a chip, and the printed circuit board contains: a trace, and a dielectric layer. The carrier includes at least an element. The trace at least includes a terminal; the trace has an upper surface, a lower surface, and a side edge, the dielectric layer includes a predetermined opening, an upper surface, a lower surface, and a side edge, wherein the predetermined opening is formed by a portion of the dielectric layer and corresponds to the terminal of the trace. And the carrier is coupled with the dielectric layer.

Methods/structures of joining package structures are described. Those methods/structures may include a first package, wherein the first package includes a first substrate section and a second substrate section. A plurality of stacked die may be disposed between the first substrate section and the second substrate section, wherein a surface of a first die of the plurality of stacked die is coplanar with a surface of the first section and with a surface of the second section. A second package is physically and electrically coupled to the first package.

A semiconductor device includes: an interposer mounted on an upper surface of a printed board; a first semiconductor element mounted on an upper surface of the interposer; a second semiconductor element mounted on the upper surface of the printed board and performing conversion between an optical signal and an electrical signal; and a bonding wire connecting a first pad and a second pad, the first pad being provided on the upper surface of the interposer, the second pad being provided on an upper surface of the second semiconductor element, the first semiconductor element lowers a speed of an electrical signal input from the second semiconductor element and outputs the electrical signal to the printed board, and increases a speed of an electrical signal and outputs the electrical signal to the second semiconductor element via the interposer and the bonding wire.

One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.

A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.

A semiconductor device is provided, which includes a semiconductor die and a redistribution layer. The redistribution layer is formed on the semiconductor die, and includes a plurality of center pads, a plurality of edge pads, and a plurality of conductive wires electrically connecting the plurality of center pads to the plurality of edge pads. Each of the plurality of conductive wires comprises at least two turning points, and an inner angle at each turning point is greater than a predetermined angle.

A semiconductor device is provided, which includes a semiconductor die and a redistribution layer. The redistribution layer is formed on the semiconductor die, and includes a plurality of center pads, a plurality of edge pads, and a plurality of conductive wires electrically connecting the plurality of center pads to the plurality of edge pads. Each of the plurality of conductive wires comprises at least two turning points, and an inner angle at each turning point is greater than a predetermined angle.

In a semiconductor device, a sealing body seals a semiconductor element, at least part of a wiring member, at least part of signal terminals, a relay substrate, and bonding wires. The bonding wires electrically connect pads of the semiconductor element and lands of the relay substrate. The wiring member has a front-face metal body. The front-face metal body includes a wiring portion and an island portion electrically isolated from the wiring portion. The semiconductor element is disposed on the wiring portion and the relay substrate is disposed on the island portion.

A semiconductor device is configured to suppress an occurrence of dielectric breakdown in the semiconductor device. The semiconductor device includes an insulating element, a conductive member on which the insulating element is mounted, and a sealing resin covering the insulating element. The conductive member includes an uneven part covered by the sealing resin. As an example, in the semiconductor device, the conductive member includes a first die pad on which the insulating element is mounted, and the uneven part includes a first region that is provided on the first die pad.

A semiconductor device includes an insulating substrate including a substrate, a metal pattern formed on an upper surface of the substrate, and a metal film formed on a lower surface of the substrate, a semiconductor element fixed on the metal pattern, a case surrounding the metal pattern and having a contact portion maintained in contact with the upper surface of the substrate, and an adhesive with which the case and a portion of the upper surface of the substrate outside a portion maintained in contact with the contact portion are bonded together, wherein a plurality of through holes are formed in a peripheral portion of the case, the through holes extending vertically through the case, and wherein the metal film exists in at least part of a place right below the contact portion.