A semiconductor device includes a vertical column of wire bonds on substrate contact fingers of the device. Semiconductor dies are mounted on a substrate, and electrically coupled to the substrate such that groups of semiconductor dies may have bond wires extending to the same contact finger on the substrate. By bonding those wires to the contact finger in a vertical column, as opposed to separate, side-by-side wire bonds on the contact finger, an area of the contact finger may be reduced.

A semiconductor structure is disclosed. The semiconductor structure includes a substrate an elastomer coupled to the substrate and a plurality of bondfingers on the elastomer. The substrate, the elastomer and the bondfingers are configured to cooperatively expand and retract.

Embodiments described herein are directed to a temporary interconnect for use in testing one or more devices (e.g., one or more dies, inductors, capacitors, etc.) formed in semiconductor package. In one scenario, a temporary interconnect acts an electrical bridge that electrically couples a contact pad on a surface of a substrate and the test pad. Coupling the contact pad and the test pad to each other enables the device(s) coupled the contact pad to be tested. Following testing, the temporary interconnect can be removed or severed so that an electrical break is formed in the conductive path between test pad and the contact pad.

A semiconductor package may include: a substrate having a first side and a second side on a same plane; a first semiconductor chip disposed over the second side of the substrate; a first one-side third semiconductor chip stack disposed over the first side of the substrate and spaced apart from the first semiconductor chip; a second semiconductor chip stack disposed over the first semiconductor chip and the first one-side third semiconductor chip stack, the second semiconductor chip stack including one or more second semiconductor chips; and a second one-side third semiconductor chip stack disposed over the second semiconductor chip stack, wherein each of the third semiconductor chip stacks includes a plurality of third semiconductor chips that are offset-stacked, offset towards the first side as the third semiconductor chips are farther from the substrate, each of the third semiconductor chip stacks being electrically connected to the substrate.

Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.

A sensor is provided, including a substrate, a chip and a sensing element. The substrate has a plate-like shape and includes a surface and an interconnect structure disposed in the substrate. The chip is embedded in the substrate and is electrically connected to the interconnect structure. The sensing element is disposed on the surface of the substrate, and is electrically connected to the chip through the interconnect structure.

A die stacking structure, a semiconductor package and a method for forming the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; and a stack of dielectric layers, extending in between the second device dies, and laterally enclosing each of the second device dies. The dielectric layers are respectively formed of a spin-on-glass (SOG) or a polymer, and a lower one of the dielectric layers has a thickness greater than a thickness of another one of the dielectric layers at a higher level.

A die stacking structure, a semiconductor package and a method for manufacturing the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; a gap profile modifier, laterally enclosing bottommost portions of the second device dies, wherein a thickness of the gap profile modifier gradually decreases away from sidewalls of the second device dies; and a dielectric material, covering the gap profile modifier and laterally surrounding the second device dies.