The present disclosure is directed to a micro module with a support structure. The micro module includes a carrier substrate having contacts and a bonding pad, a semiconductor die, and a support structure. The semiconductor die is positioned on the bonding pad and is electrically coupled to the contacts. The support structure is positioned on the bonding pad and adjacent to the semiconductor die. The support structure reinforces the bonding pad such that the bonding pad is more rigid than flexible. As a result, an external force applied to the micro module is less likely to cause the micro module to bend and damage the semiconductor die.

A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections.

A semiconductor device includes a substrate, a first adhesive layer, a first semiconductor chip, and a second adhesive layer. The first adhesive layer is provided above a first surface of the substrate and includes a plurality of types of resins having different molecular weights and a filler. The first semiconductor chip is provided above the first adhesive layer. The second adhesive layer is provided in at least a part of a first region between the substrate and the first adhesive layer, and the second adhesive layer includes at least one type of resins among the plurality of types of resins having a molecular weight smaller than a molecular weight of other types of resins among the plurality of types of resins, and a filler having a lower concentration than that of the first adhesive layer.

A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, an optically-cured dielectric layer, a plurality of block layers and a sacrificial layer. The circuit layer includes a plurality of conductive pads. The optically-cured dielectric layer has an upper surface and a lower surface opposite to the upper surface. The optically-cured dielectric layer covers the circuit layer, and first surfaces of the conductive pads are at least partially exposed from the upper surface of the optically-cured dielectric layer. The block layers are respectively disposed on the first surfaces of the conductive pads exposed by the optically-cured dielectric layer. The sacrificial layer is disposed on the optically-cured dielectric layer and covering the block layers.

A semiconductor packaging substrate is provided and includes: an insulating layer, a thinned circuit structure formed of circuit layers and conductive posts stacked on one another embedding in the insulating layer, and a supporting structure formed on the insulating layer and having at least one through hole exposing the conductive posts. As such, before a subsequent packaging operation, the packaging substrate can be electrically tested and screened so as to prevent a defective packaging substrate from being misused in the subsequent packaging operation and hence avoid the loss of normal electronic elements. A method for fabricating a semiconductor packaging substrate and a packaging process using the semiconductor packaging substrate are also provided.

A lead frame structure for connecting a semiconductor chip to a connection target includes a conductive member electrically connecting the semiconductor chip and the connection target. The conductive member includes a first bonding part having a main surface, disposed on one side of the conductive member and being bonded to the semiconductor chip, a second bonding part having a main surface, being disposed on another side of the conductive member that is spaced from the one side in one direction and being bonded to the connection target, and a joining part having a wall section intersecting the main surface of the first bonding part and the main surface of the second bonding part, the wall section joining a portion of the first bonding part to a portion of the second bonding part.

A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.

A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.

A semiconductor device is disclosed including a stack of semiconductor die on a substrate, wherein a semiconductor die in the stack is wire bonded to the substrate using dummy wire bonds. Each dummy wire bond has a stiffness so that together, the dummy wire bonds effectively pull and/or hold down the die stack against the substrate.

A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.