According to one embodiment, a semiconductor device includes: a printed wiring substrate that includes a substrate, a wiring layer on the substrate, and a first insulating layer on the wiring layer. The wiring layer includes a connection terminal and a wiring electrically connected to the connection terminal. The first insulating layer includes an opening that exposes at least a portion of the connection terminal and at least a portion of the wiring, and at least one of a protrusion portion or a recess portion, provided along an edge of the opening, that overlaps the wiring. The semiconductor device includes a semiconductor chip mounted on the printed wiring substrate; a bonding wire that electrically connects the connection terminal and the semiconductor chip; and a second insulating layer that covers the semiconductor chip, the bonding wire, and the opening.

A package substrate may include first conductive patterns, a first insulation layer and a second insulation layer. The first conductive patterns may be electrically connected with a semiconductor chip. The first insulation layer may be on an upper surface and side surfaces of each of the first conductive patterns. The first insulation layer may include at least one opening under at least one of side surfaces of the semiconductor chip. The second insulation layer may be on a lower surface of each of the first conductive patterns. Thus, a gas generated from the DAF may be readily discharged through the opening. A spreading of a crack, which may be generated at the interface between the side surface of the semiconductor chip and the molding member, toward the conductive patterns of the package substrate may be limited and/or suppressed. Adhesion between the semiconductor chip and the molding member may be reinforced.

A semiconductor package includes a frame having a first surface, a second surface opposite the first surface, and a through-hole, a first semiconductor chip in the through-hole of the frame, a second semiconductor chip on the frame, a first connection structure on the first surface of the frame and including a first redistribution structure electrically connected to the first semiconductor chip and having a third surface contacting the first surface of the frame, the first redistribution structure including a first redistribution layer and a first redistribution via, a first pad on a center portion of a fourth surface of the first redistribution structure opposite the third surface, a second pad on an edge portion of the fourth surface, a second connection structure on the second surface and comprising a second redistribution structure electrically connected to the second semiconductor chip and including a second redistribution layer and a second redistribution via, and an electrical connection metal on the first pad on the fourth surface, wherein the electrical connection metal is not on the second pad.

A semiconductor device package includes a semiconductor device in an encapsulating layer, an electrical conductor for electrical connection of the semiconductor device to an external device, and a redistribution structure for electrical connection between the semiconductor device and the electrical conductor. The redistribution structure includes dielectric layers stacked on each other in a direction extending between the encapsulating layer and the electrical conductor, wherein the dielectric layer most adjacent to the electrical conductor includes a first pattern under the electrical conductor, and circuit layers each corresponding to a respective one of the dielectric layers. The semiconductor device package further includes a conductive region disposed in the dielectric layer most adjacent to the electrical conductor according to the first pattern, and a first dielectric region, disposed in the dielectric layer most adjacent to the electrical conductor under the electrical conductor according to the first pattern, and surrounded by the conductive region.

A semiconductor device may include a first substrate, a first electrical component, a lid, a second substrate, and a second electrical component. The first substrate may include an upper surface, a lower surface, and an upper cavity in the upper surface. The first electrical component may reside in the upper cavity of the first substrate. The lid may cover the upper cavity and may include a port that permits fluid to flow between an environment external to the semiconductor device and the upper cavity. The second substrate may include the second electrical component mounted to an upper surface of the second substrate. The lower surface of the first substrate and the upper surface of the second substrate may fluidically seal the second electrical component from the upper cavity.

A printed circuit board (PCB) includes an insulating layer with an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern.

A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.

A semiconductor package may include a package substrate, a support structure on the package substrate and having a cavity therein, and at least one first semiconductor chip on the package substrate in the cavity. The support structure may have a first inner sidewall facing the cavity, a first top surface, and a first inclined surface connecting the first inner sidewall and the first top surface. The first inclined surface may be inclined with respect to a top surface of the at least one first semiconductor chip.

According to one embodiment, a semiconductor device includes a first substrate. A first semiconductor chip having a first surface facing the first substrate and a second surface opposite the first surface. The first semiconductor chip has electrodes on the first surface and is coupled to the first substrate. A first resin layer is provided at least between the first substrate and the first semiconductor chip, and covers the second surface. The first resin layer has an upper surface substantially flatter than the second surface.

A substrate includes a dielectric layer, a first metal bar, a plurality of first traces, a plurality of first openings, a second metal bar, and at least one second opening. The dielectric layer has a first major surface and a second major surface opposite to the first major surface. The first metal bar is on the first major surface. The plurality of first traces are on the first major surface. Each first trace is connected at one end to the first metal bar. The plurality of first openings expose the dielectric layer on the first major surface and intersect a first trace. The second metal bar is on the second major surface. The at least one second opening exposes the dielectric layer on the second major surface and intersects the second metal bar. The first openings are laterally offset with respect to the at least one second opening.