An LED module includes a mount board and an LED chip. The mount board includes: an insulation substrate that includes resin and glass; a first conductor, a second conductor and a third conductor; and a white resist layer. The white resist layer is provided with a first opening, a second opening and at least one third opening for exposing the first conductor, the second conductor and the third conductor, respectively. The LED module further includes a wavelength conversion layer disposed between the LED chip and the third conductor in a thickness direction of the LED chip. The wavelength conversion layer includes phosphor particles that are excited by first light emitted from the LED chip to emit second light having wavelengths greater than wavelengths of the first light.

A method for fabricating a substrate structure for packaging includes providing a core substrate, a plurality of conductive pads at a first surface of the core substrate, and a metal layer at a second surface of the core substrate opposite to the first surface; forming a conductive structure, for pasting the substrate structure onto an external component, on each of the plurality of conductive pads; forming a molding compound on the first surface of the core substrate and to encapsulate the conductive structure; and forming a plurality of packaging pads by patterning the metal layer at the second surface of the core substrate.

Disclosed are examples of integrated circuit (IC) packages. Each IC package may include a flip-chip (FC) die on a substrate, a wire bond die above the FC die, a wire bond connected to the wire bond die, and a mold on the substrate and encapsulating the FC die, the wire bond die, and the wire bond. The substrate may include least a first metallization layer includes a first substrate layer, a trace on the first substrate layer and routed within the first metallization layer to electrically couple with one or more FC interconnects of the FC die, and a bond finger pad formed on the trace. The bond finger pad may be circular. The wire bond may electrically connect to the trace such that the wire bond die is electrically coupled with the FC die through the wire bond, the bond finger pad, and the trace.

According to one embodiment, a semiconductor device includes a first substrate. A first semiconductor chip having a first surface facing the first substrate and a second surface opposite the first surface. The first semiconductor chip has electrodes on the first surface and is coupled to the first substrate. A first resin layer is provided at least between the first substrate and the first semiconductor chip, and covers the second surface. The first resin layer has an upper surface substantially flatter than the second surface.

According to one embodiment, a semiconductor device comprises a circuit board and a semiconductor package mounted on the circuit board. The semiconductor package comprises a semiconductor chip, a first connector on a bottom surface of the semiconductor package and electrically connected to the semiconductor chip, and a metal bump coupled to the first connector and electrically connected to a second connector on the circuit board. The first connector has a contact surface facing the second connector. The contact surface has a recessed portion into which the metal bump extends.

A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.

A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections.

A semiconductor package includes a package substrate having a first insulating layer, a wiring layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and covering at least a portion of the wiring layer, a pair of support members disposed to face each other on the second insulating layer of the package substrate, and a pair of semiconductor chips disposed between the pair of support members and electrically connected to the wiring layer, wherein the second insulating layer has an opening surrounding at least a portion of each of the pair of semiconductor chips.

A semiconductor package includes a package substrate which includes a substrate base and a plurality of wiring patterns, a lower semiconductor chip, and an upper semiconductor chip. The substrate base includes a chip-accommodating cavity and the plurality of wiring patterns include a plurality of bottom wiring patterns on a bottom surface of the substrate base and a plurality of top wiring patterns on a top surface of the substrate base. The lower semiconductor chip is disposed in the chip-accommodating cavity and is connected to the plurality of bottom wiring patterns through a plurality of lower bonding wires. The upper semiconductor chip includes a first portion which is attached to the lower semiconductor chip and a second portion which overhangs the lower semiconductor chip.

A package substrate includes a multilayer circuit structure, a gas-permeable structure, a heat conducting component, a first circuit layer, a second circuit layer and a build-up circuit structure. The gas-permeable structure and the heat conducting component are respectively disposed in a first and a second through holes of the multilayer circuit structure. The first and the second circuit layers are respectively disposed on an upper and a lower surfaces of the multilayer circuit structure and expose a first and a second sides of the gas-permeable structure. The build-up circuit structure is disposed on the first circuit layer and includes at least one patterned photo-imageable dielectric layer and at least one patterned circuit layer alternately stacked. The patterned circuit layer is electrically connected to the first circuit layer by at least one opening. The build-up circuit structure and the first circuit layer exposed by a receiving opening form a recess.