In various embodiments, the present disclosure provides semiconductor packages, devices, and methods. In one embodiment, a device includes a die pad, leads that are spaced apart from the die pad, and a semiconductor die on the die pad. The semiconductor die has a first surface and a second surface opposite the first surface. The second surface faces the die pad. An encapsulant is provided on the semiconductor die, the die pad and the leads, and the encapsulant has a first surface opposite the die pad and the leads, and a second surface opposite the first surface. The second surface of the encapsulant extends between the die pad and an adjacent lead. The second surface of the encapsulant is spaced apart from the first surface of the encapsulant by a first distance, and an exposed surface of the die pad is spaced apart from the first surface of the encapsulant by a second distance that is greater than the first distance.

Various embodiments of a die carrier package and a method of forming such package are disclosed. The package includes one or more dies disposed within a cavity of a carrier substrate, where a first die contact of one or more of the dies is electrically connected to a first die pad disposed on a recessed surface of the cavity, and a second die contact of one or more of the dies is electrically connected to a second die pad also disposed on the recessed surface. The first and second die pads are electrically connected to first and second package contacts respectively. The first and second package contacts are disposed on a first major surface of the carrier substrate adjacent the cavity.

An electronic device is disclosed. The electronic device includes a carrier including a first region and a second region distinct from the first region. The electronic device also includes an electronic component covering the first region and at least partially exposing the second region. The electronic device also includes a first power regulating element in the second region of the carrier and a second power regulating element. The second power regulating element is disposed adjacent to the first power regulating element and electrically connected to the electronic component through the first power regulating element to provide a first power path.

A semiconductor package includes a package substrate, the package substrate including a conductive plate, an insulating plate on the conductive plate, the insulating plate including a mounting region and a peripheral region surrounding the mounting region, and at least one capillary channel in the peripheral region, a semiconductor chip on the mounting region of the insulating plate, and a molding member on the insulating plate to cover the semiconductor chip, a portion of the molding member being in the at least one capillary channel.

A described example includes: a package substrate having a die pad with a die side surface and having an opposite backside surface, having leads arranged along two opposite sides and having die pad straps extending from two opposing ends of the die pad. The leads lie in a first plane, a portion of the die pad straps lie in a second plane that is spaced from the first plane and located closer to the die pad, and the die pad lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane. A semiconductor die is mounted to the die side surface and mold compound covers the semiconductor die, a portion of the leads, and the die side surface of the die pad, and the backside surface of the die pad exposed from the mold compound.

An insulation chip includes an element insulation layer, a first capacitor, and a second capacitor. The first capacitor includes a first front surface-side electrode plate and a first back surface-side electrode plate that are disposed opposite each other. The second capacitor includes a second front surface-side electrode plate and a second back surface-side electrode plate. The second front surface-side electrode plate and the second back surface-side electrode plate are opposed to each other. In the element insulation layer, the first back surface-side electrode plate and the second back surface-side electrode plate are electrically connected. This signal transmission device includes: a first chip including a first circuit; the insulation chip; and a second chip including a second circuit configured to perform at least one of transmission and reception of a signal with the first circuit via the insulation chip.

A described example includes: a package substrate having a die pad with a die side surface and having an opposite backside surface, having leads arranged along two opposite sides and having die pad straps extending from two opposing ends of the die pad. The leads lie in a first plane, a portion of the die pad straps lie in a second plane that is spaced from the first plane and located closer to the die pad, and the die pad lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane. A semiconductor die is mounted to the die side surface and mold compound covers the semiconductor die, a portion of the leads, and the die side surface of the die pad, and the backside surface of the die pad exposed from the mold compound.

A semiconductor package includes a package substrate, the package substrate including a conductive plate, an insulating plate on the conductive plate, the insulating plate including a mounting region and a peripheral region surrounding the mounting region, and at least one capillary channel in the peripheral region, a semiconductor chip on the mounting region of the insulating plate, and a molding member on the insulating plate to cover the semiconductor chip, a portion of the molding member being in the at least one capillary channel.

A semiconductor device includes first and second leads, a semiconductor element, and conductive members. The first lead includes a base including a first surface on which the semiconductor element is mounted. Each conductive member includes first and second end portions. The semiconductor element includes first and second obverse-surface electrodes formed on an element obverse surface. A first end portion of each conductive member is bonded to the first or the second obverse-surface electrode. The second lead includes first and second portions of an elongated shape. In plan view, the first portion is located on a first side in a first direction with respect to the base. The second portion is located on a first side in a second direction with respect to the base, extending in the first direction. The conductive members include a first conductive member whose second end portion is bonded to the second portion.

The present disclosure relates to a package structure and a method for forming the same. The package structure includes: a plurality of second interconnect metal traces and bonding pads in a same plane; a plurality of first surface metal bumps and first interconnect metal traces disposed on the first surfaces of the second interconnect metal traces; a plurality of passive devices correspondingly mounted on top surfaces of the first surface metal bumps; a first molding layer encapsulating the passive devices, the first surface metal bumps, and the first interconnect metal traces, and covering the first surfaces of the bonding pads; a dielectric layer covering the second surfaces of the second interconnect metal traces and a bottom surface of the first molding layer; a first chip having wire bonding pads; and metal wires electrically connecting the wire bonding pads to the second surfaces of the bonding pads.