A semiconductor device according to the present disclosure includes: a semiconductor element; a plurality of conductive members each electrically connected to the semiconductor element and each extending upward; a sealing resin to seal the semiconductor element and the conductive member and to form a protrusion that covers a perimeter of a tip portion of each of the plurality of conductive members; a control substrate provided with a through hole into which the protrusion is inserted, the control substrate having a control electrode; and a flexible wiring to connect the control electrode and the tip portion of the conductive member to each other, the flexible wiring having flexibility. With such a configuration, a trouble due to external force or stress applied to the semiconductor device or the semiconductor package can be prevented and the semiconductor device or the semiconductor package having an excellent durability can be obtained.

A power semiconductor device includes a base plate; a Si chip including a Si substrate, the Si chip attached to the base plate; a first metal preform pressed with a first press pin against the Si chip; a wide bandgap material chip comprising a wide bandgap substrate and a semiconductor switch provided in the wide bandgap substrate, the wide bandgap material chip attached to the base plate; and a second metal preform pressed with a second press pin against the wide bandgap material chip; the Si chip and the wide bandgap material chip are connected in parallel via the base plate and via the first press pin and the second press pin; the first metal preform is adapted for forming a conducting path through the Si chip, when heated by an overcurrent; and the second metal preform is adapted for forming an temporary conducting path through the wide bandgap material chip or an open circuit, when heated by an overcurrent.

Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

A QFN package includes a copper lead frame. The copper lead frame includes a die paddle. A die is fixed on the die pad. A coolant passage is disposed within the die paddle. An inlet passage connects to one end of the coolant passage. An outlet passage connects to another end of the coolant passage. A mold compound encapsulates the copper lead frame and the die.

The semiconductor device package comprises a die carrier, at least one semiconductor die disposed on the carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier, an encapsulant disposed above the semiconductor die, an electrical connector electrically connected with the contact pad, a drilling screw screwed through the encapsulant and connected with the electrical connector.

Methods are provided for forming an IC power package including a power MOSFET device, a microprocessor/driver, and/or other discrete electronics. A lead frame may be etched to form a half-etch lead frame defining component attach structures at the top side of the lead frame. A power MOSFET may be mounted to a die attach pad defined in the half-etch lead frame, and the structure may be overmolded. The top of the overmolded structure may be grinded to reduce a thickness of the power MOSFET and expose a top surface of the MOSFET through the surrounding mold compound. A conductive contact may be formed on a top surface of the MOSFET. Selected portions of the half-etch lead frame may be etched from the bottom-up to separate the MOSFET from other package components, and to define a plurality of package posts for solder-mounting the package to a PCB.

A semiconductor device assembly is provided. The assembly includes a substrate having a plurality of contact pads disposed at a coupling surface. A semiconductor die is coupled with the substrate at the plurality of contact pads, and a liquid-repelling material resistant to wetting by an underfill material is disposed at the coupling surface of the substrate surrounding a periphery of the semiconductor die. The underfill material is disposed between the semiconductor die and the substrate. The underfill material includes a fillet between the semiconductor die and the liquid-repelling material. As a result, the expansion of the underfill material beyond the semiconductor die may be controlled.

The present disclosure is directed to a leadframe package with a surface mounted semiconductor die coupled to leads of the leadframe package through wire bonding. The leads are partially exposed outside the package and configured to couple to another structure, like a printed circuit board (PCB). The exposed portions, namely outer segments, of the leads include a plating or coating layer of a material that enhances the solder wettability of the leads to the PCB through solder bonding. The enclosed portions, namely inner segments, of the leads do not include the plating layer of the outer segment and, thus, include a different surface material or surface finish.

A semiconductor light emitting apparatus includes: a stem part having a stem base, a lead terminal, and a metal member having a closed shape, the stem base having an inner portion having a first face, a second face and an opening extending in a first direction from the first face to the second face, and an outer portion surrounding the inner portion, the inner and outer portions being arranged along a reference plane intersecting the first direction, the lead terminal being supported in the opening, and the metal member being disposed on the outer portion so as to surround the inner portion and having a first portion supported by a top face of the outer portion, and a second portion extending outward with reference to an edge of the outer portion; a semiconductor optical element disposed on the inner portion; and a cap disposed on the metal member.

Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.