A process of detecting a thickness of a film layer to be processed or a depth of etching by using a result of detection of a signal indicating intensity of interference light having a plurality of wavelengths formed at a plurality of time instants from when plasma is formed to when the etching is completed. A start time instant is detected by using an amount of change in the intensity of the interference light. Then, a remaining film thickness or the etching amount at an arbitrary time instant is detected from a result of comparing actual data indicating the intensity of the interference light at the arbitrary time instant during the processing after the start time instant with a plurality of pieces of data for detection of the intensity of the interference light obtained in advance and associated with values of a the film thicknesses or the depths of etching.

In one embodiment, a system includes an RF source and an RF impedance matching circuit receiving RF power from the RF source. The matching circuit includes at least one variable reactance element, a sensor operably coupled to a component of the matching circuit, and a control circuit. The control circuit receives a signal from the sensor indicative of a parameter value. Upon determining the parameter value meets a first predetermined condition, the control circuit transmits a control signal to the RF source causing the RF source to carry out a power control scheme. The power control scheme causes the RF source to reduce or maintain the RF power without turning off the RF power.

According to one embodiment, a substrate processing device includes a stage configured to mount a substrate, a mold having a first surface facing an upper surface of an outer peripheral edge of the substrate and a second surface facing a side surface of an outer peripheral continuous with the upper surface of the outer peripheral edge, a mold moving mechanism configured to move the mold to bring the first surface close to the upper surface of the outer peripheral edge of the substrate and the second surface close to the side surface of the outer peripheral of the substrate, and a nozzle arranged in the mold, wherein the nozzle ejects resist.

Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.

Embodiments of the present disclosure generally relate to methods for etching materials. In one or more embodiments, the method includes positioning a substrate in a process volume of a process chamber, where the substrate includes a metallic ruthenium layer disposed thereon, and exposing the metallic ruthenium layer to an oxygen plasma to produce a solid ruthenium oxide on the metallic ruthenium layer and a gaseous ruthenium oxide within the process volume. The method also includes exposing the solid ruthenium oxide to a secondary plasma to convert the solid ruthenium oxide to either metallic ruthenium or a ruthenium oxychloride compound. The metallic ruthenium is in a solid state on the metallic ruthenium layer or the ruthenium oxychloride compound is in a gaseous state within the process volume.

In certain embodiments, a method of processing a semiconductor structure includes forming a patterned layer over a copper layer to be etched. The copper layer is disposed over a substrate. The method includes patterning the copper layer, using the patterned layer as an etch mask, by performing a cyclic etch process to form a recess in the copper layer. The cyclic etch process includes forming, in a first etch step, a passivation layer on an exposed surface of the copper layer by exposing the exposed surface of the copper layer to a chlorine gas. The passivation layer replaces at least a portion of a surface layer of the copper layer. The cyclic etch process includes subsequently etching, in a second etch step, the passivation layer using a first plasma that includes a noble gas. Each cycle of the cyclic etch process extends the recess in the copper layer.

A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma etching process comprises applying pulsed bias voltage and RF voltage with pulsed power.

In one embodiment, a method of matching an impedance is disclosed. An impedance matching network is coupled between a radio frequency (RF) source and a plasma chamber. The matching network includes a variable reactance element (VRE) having different positions for providing different reactances. The RF source has an RF source control circuit carrying out a power control scheme to control a power delivered to the matching network. Based on a determined parameter, a new position for the VRE is determined to reduce a reflected power at the RF input of the matching network. The matching network provides a notice signal to the RF source indicating the VRE will be altered. In response to the notice signal, the RF source control circuit alters the power control scheme. While the power control scheme is altered, the VRE is altered to the new position.

Provided is a plasma etching method which enables etching with high accuracy while controlling and reducing surface roughness of a transition metal film. The etching is performed for the transition metal film, which is formed on a sample and contains a transition metal element, by a first step of isotropically generating a layer of transition metal oxide on a surface of the transition metal film while a temperature of the sample is maintained at 100° C. or lower, a second step of raising the temperature of the sample to a predetermined temperature of 150° C. or higher and 250° C. or lower while a complexation gas is supplied to the layer of transition metal oxide, a third step of subliming and removing a reactant generated by an reaction between the complexation gas and the transition metal oxide formed in the first step while the temperature of the sample is maintained at 150° C. or higher and 250° C. or lower, and a fourth step of cooling the sample.