A plasma processing method which can realize a reduction of process variation in the first one of lot processing includes a first step of supplying gas to a processing chamber and a second step of etching the sample by using plasma after the first step. The gas is a gas containing a carbon element and a hydrogen element, a gas containing a chlorine element, or a mixed gas containing all of the gases used in the second step.

An atomic layer etching method capable of precisely etching a metal thin film at units of atomic layer from a substrate including the metal thin film, includes forming a metal layer on a substrate, and etching at least a portion of the metal layer. The etching at least a portion of the metal layer includes at least one etching cycle. The at least one etching cycle includes supplying an active gas onto the metal layer, and supplying an etching support gas after supplying the active gas. The etching support gas is expressed by the following general formula

##STR00001##

wherein each of R1, R2, R3, R4 and R5 independently includes hydrogen or a C.sub.1-C.sub.4 alkyl group, and N is nitrogen.

A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.

In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

Semiconductor devices, methods of manufacturing the semiconductor device and tools are disclosed herein. Some methods include providing an electrostatic chuck and placing an edge ring adjacent to the electrostatic chuck. The electrostatic chuck includes a first electrode to generate a sheath at a first distance over the electrostatic chuck. The edge ring includes a coil and a second electrode to generate an electric field control to maintain a portion of the sheath over the edge ring in a coplanar orientation with the portion of the sheath over the electrostatic chuck.

A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.

A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

Provided are methods of manufacturing an integrated circuit device including depositing a conductive layer on a substrate, patterning the conductive layer to expose regions of the conductive layer, etching a first portion of the exposed regions of the conductive layer, forming a first passivation layer on a sidewall of the first etched portion, etching a second portion of the exposed regions of the conductive layer, and forming a second passivation layer on a sidewall of the second etched portion.

Embodiments include a contact structure and method of forming the same where the contact structure is deliberately positioned near the end of a metallic line. An opening is formed in an insulating structure positioned over the metallic line and then the opening is extended into the metallic line by an etching process. In the etching process, the line end forces etchant to concentrate back away from the line end, causing lateral etching of the extended opening. A subsequent contact is formed in the opening and enlarged opening.

Exemplary methods of etching may include flowing a fluorine-containing precursor and a secondary gas into a processing region of a semiconductor processing chamber. The secondary gas may be or include oxygen or nitrogen. A flow rate ratio of the fluorine-containing precursor to the secondary gas may be greater than or about 1:1. The methods may include contacting a substrate with the fluorine-containing precursor and the secondary gas. The substrate may include an exposed metal. The substrate may define a high aspect-ratio structure. The methods may include etching the exposed metal within the high aspect-ratio structure.