A semiconductor package device includes a carrier, a first electronic component, and a conductive element on the carrier. The first electronic component is over the carrier. The conductive element is on the carrier and electrically connects the first electronic component to the carrier. The conductive element includes at least one conductive particle and a solder material covering the conductive particle, and the conductive particle includes a metal core, a barrier layer covering the metal core, and a metal layer covering the barrier layer.

A semiconductor package device includes a carrier, a first electronic component, and a conductive element on the carrier. The first electronic component is over the carrier. The conductive element is on the carrier and electrically connects the first electronic component to the carrier. The conductive element includes at least one conductive particle and a solder material covering the conductive particle, and the conductive particle includes a metal core, a barrier layer covering the metal core, and a metal layer covering the barrier layer.

An electronic apparatus includes: a first electronic component including a first electrode; solder on the first electrode; and a phase containing In, Ag, and Cu, the phase being dispersed and included in the solder. And a method for manufacturing an electronic apparatus, the method includes: forming solder on a first electrode of a first component, the solder including a phase containing In, Ag, and Cu, the phase being dispersed in the solder.

An electronic apparatus includes: a first electronic component including a first electrode; solder on the first electrode; and a phase containing In, Ag, and Cu, the phase being dispersed and included in the solder. And a method for manufacturing an electronic apparatus, the method includes: forming solder on a first electrode of a first component, the solder including a phase containing In, Ag, and Cu, the phase being dispersed in the solder.

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

Produced is a metal ball which suppresses an emitted dose. Contained are the steps of melting a pure metal by heating the pure metal at a temperature which is higher than a boiling point of an impurity to be removed, higher than a melting point of the pure metal, and lower than a boiling point of the pure metal, the pure metal containing a U content of 5 ppb or less, a Th content of 5 ppb or less, purity of 99.9% or more and 99.995% or less, and a Pb or Bi content or a total content of Pb and Bi of 1 ppm or more, and the pure metal having the boiling point higher than the boiling point at atmospheric pressure of the impurity to be removed; and sphering the molten pure metal in a ball.

Produced is a metal ball which suppresses an emitted dose. Contained are the steps of melting a pure metal by heating the pure metal at a temperature which is higher than a boiling point of an impurity to be removed, higher than a melting point of the pure metal, and lower than a boiling point of the pure metal, the pure metal containing a U content of 5 ppb or less, a Th content of 5 ppb or less, purity of 99.9% or more and 99.995% or less, and a Pb or Bi content or a total content of Pb and Bi of 1 ppm or more, and the pure metal having the boiling point higher than the boiling point at atmospheric pressure of the impurity to be removed; and sphering the molten pure metal in a ball.

According to aspects provided herein, a semiconductor device may include a bump providing improved reliability and reduced size. In some aspects, a conductive pad may be formed on a substrate, and a conductive support layer, which may be a pillar, may be formed on the conductive pad. An intermetallic compound (IMC) layer may be formed on the conductive support layer, and a solder layer may be formed on the IMC layer. In some aspects, the conductive support layer may be of a smaller width than the IMC layer. In some aspects, the conductive support layer may have side surfaces which are wider at the solder side than at the conductive pad side. In some aspects, other layers may be formed, such as a seed layer between the conductive pad and the conductive support layer, or a barrier layer between the conductive support layer and the IMC layer.

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.