A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

Improved electrical and thermal properties of solder alloys are achieved by the use of micro-additives in solder alloys to engineer the electrical and thermal properties of the solder alloys and the properties of the reaction layers between the solder and the metal surfaces. The electrical and thermal conductivity of alloys and that of the reaction layers between the solder and the -metal surfaces can be controlled over a wide range of temperatures. The solder alloys produce stable microstructures wherein such stable microstructures of these alloys do not exhibit significant changes when exposed to changes in temperature, compared to traditional interconnect materials.

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

Provided is a method of fabricating a semiconductor package. The method of fabricating the semiconductor package include preparing a lower element including a lower substrate, a lower electrode, an UBM layer, and a reducing agent layer, providing an upper element including an upper substrate, an upper electrode, and a solder bump layer, providing a pressing member on the upper substrate to press the upper substrate to the lower substrate, and providing a laser beam passing through the pressing member to bond the upper element to the lower element.

An electronic device includes a first electronic part, a second electronic part opposite the first electronic part, and a bonding portion between the first electronic part and the second electronic part. The bonding portion contains a solder containing a substance whose crystal structure reversibly changes in temperature rise and fall processes which accompany the operation of the electronic device or electronic equipment including the electronic device. A change in the crystal structure of the substance contained in the solder promotes recovery and recrystallization of the solder in the temperature rise and fall processes which accompany the operation of the electronic device or the electronic equipment. As a result, the coarsening of crystal grains in the solder is suppressed.

An electronic device includes a first electronic part, a second electronic part opposite the first electronic part, and a bonding portion between the first electronic part and the second electronic part. The bonding portion contains a solder containing a substance whose crystal structure reversibly changes in temperature rise and fall processes which accompany the operation of the electronic device or electronic equipment including the electronic device. A change in the crystal structure of the substance contained in the solder promotes recovery and recrystallization of the solder in the temperature rise and fall processes which accompany the operation of the electronic device or the electronic equipment. As a result, the coarsening of crystal grains in the solder is suppressed.

A chip package including a substrate is provided. A sensing region or device region of the substrate is electrically connected to a conducting pad. A first insulating layer is disposed on the substrate. A redistribution layer is disposed on the first insulating layer. A first portion and a second portion of the redistribution layer are electrically connected to the conducting pad. A second insulating layer conformally extends on the first insulating layer, and covers side surfaces of the first portion and the second portion. A protection layer is disposed on the second insulating layer. A portion of the second insulating layer is located between the protection layer and the first insulating layer. A method of forming the chip package is also provided.

A chip package including a substrate is provided. A sensing region or device region of the substrate is electrically connected to a conducting pad. A first insulating layer is disposed on the substrate. A redistribution layer is disposed on the first insulating layer. A first portion and a second portion of the redistribution layer are electrically connected to the conducting pad. A second insulating layer conformally extends on the first insulating layer, and covers side surfaces of the first portion and the second portion. A protection layer is disposed on the second insulating layer. A portion of the second insulating layer is located between the protection layer and the first insulating layer. A method of forming the chip package is also provided.

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.