A power module package is provided. The power module package may include: a first substrate; a second substrate; a semiconductor chip disposed between the first substrate and the second substrate; and a mutual-connection layer that is formed between the semiconductor chip and the second substrate and provides conductive connection between the semiconductor chip and the second substrate.

A technique for fabricating a bump structure is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared, in which the pads includes first conductive material. A metallic adhesion layer is coated on each pad. A bump base is formed on each pad by sintering conductive particles using a mold layer, in which the conductive particles includes second conductive material different from the first conductive material.

A power module package is provided. The power module package may include: a first substrate; a second substrate; a semiconductor chip disposed between the first substrate and the second substrate; and a mutual-connection layer that is formed between the semiconductor chip and the second substrate and provides conductive connection between the semiconductor chip and the second substrate.

A power module package is provided. The power module package may include: a first substrate; a second substrate; a semiconductor chip disposed between the first substrate and the second substrate; and a mutual-connection layer that is formed between the semiconductor chip and the second substrate and provides conductive connection between the semiconductor chip and the second substrate.

An SIP module includes a plurality of electrical components mounted to an interconnect substrate. The electrical components and interconnect substrate are covered by an encapsulant. A conductive post is formed through the encapsulant. A plurality of openings is formed in the encapsulant by laser in a form of a circuit pattern. A conductive material is deposited over a surface of the encapsulant and into the openings to form an electrical circuit pattern. A portion of the conductive material is removed by a grinder to expose the electrical circuit pattern. The grinding operation planarizes the surface of the encapsulant and the electrical circuit pattern. The electrical circuit pattern can be a trace, contact pad, RDL, or other interconnect structure. The electrical circuit pattern can also be a shielding layer or antenna. An electrical component is disposed over the SIP module and electrical circuit pattern.

An SIP module includes a plurality of electrical components mounted to an interconnect substrate. The electrical components and interconnect substrate are covered by an encapsulant. A conductive post is formed through the encapsulant. A plurality of openings is formed in the encapsulant by laser in a form of a circuit pattern. A conductive material is deposited over a surface of the encapsulant and into the openings to form an electrical circuit pattern. A portion of the conductive material is removed by a grinder to expose the electrical circuit pattern. The grinding operation planarizes the surface of the encapsulant and the electrical circuit pattern. The electrical circuit pattern can be a trace, contact pad, RDL, or other interconnect structure. The electrical circuit pattern can also be a shielding layer or antenna. An electrical component is disposed over the SIP module and electrical circuit pattern.

Methods for die attachment of multichip and single components including flip chips may involve printing a sintering paste on a substrate or on the back side of a die. Printing may involve stencil printing, screen printing, or a dispensing process. Paste may be printed on the back side of an entire wafer prior to dicing, or on the back side of an individual die. Sintering films may also be fabricated and transferred to a wafer, die or substrate. A post-sintering step may increase throughput.

Methods for die attachment of multichip and single components including flip chips may involve printing a sintering paste on a substrate or on the back side of a die. Printing may involve stencil printing, screen printing, or a dispensing process. Paste may be printed on the back side of an entire wafer prior to dicing, or on the back side of an individual die. Sintering films may also be fabricated and transferred to a wafer, die or substrate. A post-sintering step may increase throughput.

Provided are a hybrid bonding structure, a solder paste composition, a semiconductor device, and a method of manufacturing the semiconductor device. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste includes a transient liquid phase. The transient liquid phase includes a core and a shell on a surface of the core. A melting point of the shell may be lower than a melting point of the core. The core and the shell are configured to form an intermetallic compound in response to the transient liquid phase at least partially being at a temperature that is within a temperature range of about 20° C. to about 190° C.

Provided are a hybrid bonding structure, a solder paste composition, a semiconductor device, and a method of manufacturing the semiconductor device. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste includes a transient liquid phase. The transient liquid phase includes a core and a shell on a surface of the core. A melting point of the shell may be lower than a melting point of the core. The core and the shell are configured to form an intermetallic compound in response to the transient liquid phase at least partially being at a temperature that is within a temperature range of about 20° C. to about 190° C.