A method of manufacturing an organic light-emitting display apparatus includes: forming a lift-off layer on a substrate including a first electrode, the lift-off layer including a fluoropolymer; forming a pattern layer on the lift-off layer; etching the lift-off layer between patterns of the pattern layer by utilizing a first solvent to expose the first electrode; forming an organic functional layer on the first electrode and the pattern layer, the organic functional layer including an emission layer; removing remaining portions of the lift-off layer by utilizing a second solvent; and forming a second electrode on the organic functional layer.

A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

A method includes receiving a plurality of sets of sensor data associated with a processing chamber of a substrate processing system. Each of the plurality of sets of sensor data comprises a corresponding sensor value of the processing chamber mapped to a corresponding spacing value of the processing chamber. The method further includes providing the plurality of sets of sensor data as input to a trained machine learning model. The method further includes obtaining, from the trained machine learning model, one or more outputs indicative of a health of the processing chamber. The method further includes causing, based on the one or more outputs, performance of one or more corrective actions associated with the processing chamber.

This disclosure teaches methods for making high-temperature superconducting striated tape combinations and the product high-temperature superconducting striated tape combinations. This disclosure describes an efficient and scalable method for aligning and bonding two superimposed high-temperature superconducting (HTS) filamentary tapes to form a single integrated tape structure. This invention aligns a bottom and top HTS tape with a thin intervening insulator layer with microscopic precision, and electrically connects the two sets of tape filaments with each other. The insulating layer also reinforces adhesion of the top and bottom tapes, mitigating mechanical stress at the electrical connections. The ability of this method to precisely align separate tapes to form a single tape structure makes it compatible with a reel-to-reel production process.

An array substrate, a manufacturing method thereof, and a short circuit repair method are provided. The array substrate includes at least one switch unit, wherein each of the switch unit includes a first thin film transistor (TFT) set and a second TFT set, a hollow area is disposed on a first metal layer, a semiconductor layer includes a first area corresponding to the first TFT set and a second area corresponding to the second TFT set, and a vertical projection of an area between the first area and the second area on a substrate completely covers a vertical projection of the hollow area on the substrate.

Stator cores and methods for fabricating stator cores are provided. An exemplary stator core includes a stack of laminations. Each lamination in the stack of laminations comprises a yoke and a plurality of tooth segments fixed to the yoke.

A pressure die casting process and its machine are described to produce a highly efficient copper rotor for AC induction motors widely used in various industries. The pressure die casting process and the machine facilitate improvement in efficiency and performance of AC induction motors by providing maximum filling of copper with minimum porosity. Thus, a compact and convenient method is provided to cast a wide range of copper rotors of various extensive length.

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first type in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line in a third layer between the first and second layers. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate includes an upper portion and a lower portion, and the first conductive line crosses the first gate between the upper portion and the lower portion.

There is provided a method for manufacturing a SiC device wafer comprising the steps: a) slicing and polishing a SiC boule to thicker substrates compared to the usual thickness in the prior art, b) creating a device wafer on the substrate, c) removing the device wafer from the remaining substrate, d) adding SiC to the remaining substrate so that the original thickness of the substrate is essentially restored, and repeating steps b)-d). The removal of the device wafer can be made for instance by laser slicing. Advantages include that the SiC material loss is significantly decreased and the boule material used for device wafers is considerably increased, the substrates become more stable especially during high temperature processes, the warp and bow is reduced, the risk of breakage is decreased.