Patent classifications
Y10S438/977
VERTICAL STRUCTURE LEDS
A light-emitting device can include a conductive support structure comprising a metal; a GaN-based semiconductor structure disposed on the conductive support structure, the GaN-based semiconductor structure including a p-type GaN-based layer, a GaN-based active layer and an n-type GaN-based layer, in which the GaN-based semiconductor structure has a first surface, a side surface and a second surface, in which the first surface, relative to the second surface, is proximate to the conductive support structure, in which the second surface is opposite to the first surface, in which the conductive support structure is thicker than the p-type GaN-based semiconductor layer, and the conductive support structure is thicker than the n-type GaN-based semiconductor layer; a p-type electrode disposed on the conductive support structure; an n-type electrode disposed on the second surface of the GaN-based semiconductor structure; and a passivation layer disposed on the side surface and the second surface of the GaN-based semiconductor structure.
Vertical structure LEDs
A method for manufacturing a light emitting diode can include forming a GaN-based semiconductor structure with a thickness of less than 5 microns on a substrate, the GaN-based semiconductor structure having a p-type GaN-based semiconductor layer; an active layer on the p-type GaN-based semiconductor layer; and an n-type GaN-based semiconductor layer on the active layer; forming a p-type electrode having multiple metal layers on the GaN-based semiconductor structure; forming a metal support layer on the p-type electrode; removing the substrate from the GaN-based semiconductor structure to expose an upper surface of the GaN-based semiconductor structure; forming an n-type electrode on a flat portion produced by polishing the exposed upper surface of the GaN-based semiconductor structure, not only with overlapping at least a portion of the p-type electrode in a thickness direction of the GaN-based semiconductor structure but also with contacting the flat portion; and forming an insulating layer on the upper surface of the GaN-based semiconductor structure and on an entire side surface of the GaN-based semiconductor structure, in which a first part formed on the upper surface of the GaN-based semiconductor structure in the insulating layer contacts the upper surface of the GaN-based semiconductor structure and a side surface of the n-type electrode, and a second part formed on the entire side surface of the GaN-based semiconductor structure in the insulating layer does not contact the n-type electrode.
Vertical structure LEDs
A method of manufacturing a light emitting device can include forming an n-type GaN-based layer on a sapphire substrate; forming a GaN-based active layer on the n-type GaN-based layer; forming a p-type GaN-based layer on the GaN-based active layer; forming a p-type electrode on the p-type GaN-based layer; forming a metal substrate on the p-type electrode; removing the sapphire substrate; forming an n-type electrode on the n-type GaN-based layer; forming a passivation layer on a side surface of the p-type GaN-based layer, a side surface of the GaN-based active layer, a side surface of the n-type GaN-based layer, an upper surface of the n-type GaN-based layer, a side surface of the n-type electrode, and an upper surface of the n-type electrode after the forming the n-type electrode; and forming an open space to expose the n-type electrode by patterning the passivation layer.
VERTICAL STRUCTURE LEDS
A method of manufacturing a light emitting device can include forming an n-type GaN-based layer on a sapphire substrate; forming a GaN-based active layer on the n-type GaN-based layer; forming a p-type GaN-based layer on the GaN-based active layer; forming a p-type electrode on the p-type GaN-based layer; forming a metal substrate on the p-type electrode; removing the sapphire substrate; forming an n-type electrode on the n-type GaN-based layer; forming a passivation layer on a side surface of the p-type GaN-based layer, a side surface of the GaN-based active layer, a side surface of the n-type GaN-based layer, an upper surface of the n-type GaN-based layer, a side surface of the n-type electrode, and an upper surface of the n-type electrode after the forming the n-type electrode; and forming an open space to expose the n-type electrode by patterning the passivation layer.
Three dimensional device integration method and integrated device
A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.
VERTICAL STRUCTURE LEDS
A method for manufacturing a light emitting diode can include forming a GaN-based semiconductor structure with a thickness of less than 5 microns on a substrate, the GaN-based semiconductor structure having a p-type GaN-based semiconductor layer; an active layer on the p-type GaN-based semiconductor layer; and an n-type GaN-based semiconductor layer on the active layer; forming a p-type electrode having multiple metal layers on the GaN-based semiconductor structure; forming a metal support layer on the p-type electrode; removing the substrate from the GaN-based semiconductor structure to expose an upper surface of the GaN-based semiconductor structure; forming an n-type electrode on a flat portion produced by polishing the exposed upper surface of the GaN-based semiconductor structure, not only with overlapping at least a portion of the p-type electrode in a thickness direction of the GaN-based semiconductor structure but also with contacting the flat portion; and forming an insulating layer on the upper surface of the GaN-based semiconductor structure and on an entire side surface of the GaN-based semiconductor structure, in which a first part formed on the upper surface of the GaN-based semiconductor structure in the insulating layer contacts the upper surface of the GaN-based semiconductor structure and a side surface of the n-type electrode, and a second part formed on the entire side surface of the GaN-based semiconductor structure in the insulating layer does not contact the n-type electrode.
SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE
A method of fabricating a semiconductor device includes forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate.
Vertical structure LEDs
A light emitting diode can include a metal support layer: a GaN-based semiconductor structure having a less than 5 microns thickness on the metal support layer, the GaN-based semiconductor structure including a p-type GaN-based semiconductor layer, an active layer on the p-type GaN-based semiconductor layer, and an n-type GaN-based semiconductor layer on the active layer; a p-type electrode on the metal support layer and including a plurality of metal layers; an n-type electrode on a flat portion of an upper surface of the GaN-based semiconductor structure, and the n-type electrode contacts the flat portion; a metal pad layer on the n-type electrode; and an insulating layer including a first part disposed on the upper surface of the GaN-based semiconductor structure, and a second part disposed on an entire side surface of the GaN-based semiconductor structure, in which the metal pad layer includes a first portion having a flat bottom surface on the n-type electrode, and a second portion having stepped surfaces.
Semiconductor device fabrication method and semiconductor device
A method of fabricating a semiconductor device includes forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate.
Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound
A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via.