Patent classifications
Y10S977/943
Nanomagnetic network structures and a method of reconfigurable operation based on magnetization dynamics
A nanomagnetic structure and a method of fabricating a nanomagnetic structure. The nanomagnetic comprises two or more nanomagnetic material elements, each nanomagnetic material element having a respective predetermined geometric shape such that the nanomagnetic structure exhibits different stable ground states initializable by magnetic fields applied across the nanomagnetic structure in respective different directions; wherein the nanomagnetic material elements are disposed relative to each other such that the magnetic structure exhibits a difference in effective internal magnetic field strength between the different stable ground states. Advantageously, this variation in the internal magnetic field strength is the key for distinct dynamic response associated with the different magnetic ground states. Reconfigurable operation has been shown based on this magnetization dynamics in example embodiments.
Substrate treatment method, computer readable storage medium and substrate treatment system
A substrate treatment method includes: forming a plurality of circular patterns of a resist film on a substrate; thereafter applying a first block copolymer; then phase-separating the first block copolymer into a hydrophilic polymer and a hydrophobic polymer; thereafter selectively removing the hydrophilic polymer; then selectively removing the resist film from a top of the substrate; thereafter applying a second block copolymer to the substrate; then phase-separating the second block copolymer into a hydrophilic polymer and a hydrophobic polymer; and thereafter selectively removing the hydrophilic polymer from the phase-separated second block copolymer. A ratio of a molecular weight of the hydrophilic polymer in the first block copolymer and the second block copolymer is 20% to 40%.
Low power embedded one-time programmable (OTP) structures
Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.
Tunable voltage margin access diodes
The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.
Magnetic devices including film structures
A device including a magnetic structure, the magnetic structure having a substrate adjacent surface and a second, opposing surface, the magnetic structure having a near field transducer (NFT), wherein the NFT includes gold or an alloy thereof, and is positioned at the second surface an overcoat structure; and a film structure, the film structure positioned between the magnetic structure and the overcoat structure, the film structure having a total thickness of not greater than about 100 , and the film structure including: a first interfacial structure having a first and a second opposing surface; a second interfacial structure having a first and a second opposing surface; and an intermediate structure wherein the first surface of the first interfacial structure is positioned adjacent the NFT of the magnetic structure, and the second surface of the second interfacial structure is positioned adjacent the overcoat structure, and the intermediate structure is positioned between the first interfacial structure and the second interfacial structure, and wherein the first interfacial structure includes one or more rare earth elements, one or more alkaline earth metals, one or more alkali metals, or a combination thereof.
Tunable voltage margin access diodes
The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.
ADVANCED PROCESSING APPARATUS
A processing element for an advanced processing apparatus. The processing element comprises a silicon-insulator interface and a confining arrangement for confining one or more quantum dots in the semiconductor. The processing element has also a control arrangement for controlling a quantum property of the one or more quantum dots and operate the one or more quantum dots as a qubit to perform quantum processing.
Nanoscale Device Comprising an Elongated Crystalline Nanostructure
The present disclosure relates to nanoscale device comprising an elongated crystalline nanostructure, such as a nanowire crystal, a nanowhisker crystal or a nanorod crystal, and a method for producing thereof. One embodiment relates to a nanoscale device comprising an elongated crystalline semiconductor nanostructure, such as a nanowire (crystal) or nanowhisker (crystal) or nanorod (crystal), having a plurality of substantially plane side facets, a crystalline structured first facet layer of a superconductor material covering at least a part of one or more of said side facets, and a second facet layer of a superconductor material covering at least a part of the first facet layer, the superconductor material of the second facet layer being different from the superconductor material of the first facet layer, wherein the crystalline structure of the semiconductor nanostructure is epitaxially matched with the crystalline structure of the first facet layer on the interface between the two crystalline structures.
Semiconductor Josephson Junction and a Transmon Qubit Related Thereto
The present disclosure relates to semiconductor based Josephson junctions and their applications within the field of quantum computing, in particular a tuneable Josephson junction device has been used to construct a gateable transmon qubit. One embodiment relates to a Josephson junction comprising an elongated hybrid nanostructure comprising superconductor and semiconductor materials and a weak link, wherein the weak link is formed by a semiconductor segment of the elongated hybrid nanostructure wherein the superconductor material has been removed to provide a semiconductor weak link.
SUBSTRATE TREATMENT METHOD, COMPUTER READABLE STORAGE MEDIUM AND SUBSTRATE TREATMENT SYSTEM
A substrate treatment method includes: forming a plurality of circular patterns of a resist film on a substrate; thereafter applying a first block copolymer; then phase-separating the first block copolymer into a hydrophilic polymer and a hydrophobic polymer; thereafter selectively removing the hydrophilic polymer; then selectively removing the resist film from a top of the substrate; thereafter applying a second block copolymer to the substrate; then phase-separating the second block copolymer into a hydrophilic polymer and a hydrophobic polymer; and thereafter selectively removing the hydrophilic polymer from the phase-separated second block copolymer. A ratio of a molecular weight of the hydrophilic polymer in the first block copolymer and the second block copolymer is 20% to 40%.