Patent classifications
Y10T29/49124
Method for suppressing material warpage by means of pressure difference
A method for suppressing material warpage by means of a pressure difference comprises the following steps: a. preparing a plurality of carrier boards; b. preparing a plurality of carrier board pressing devices having an upper surface and a lower surface on which at least one air bag is provided; c. adjusting the processing chamber to be a working temperature and a working pressure, so that the carrier boards and the carrier board pressing devices placed therein are surrounded by the working temperature and the working pressure; d. effectively suppressing warpage of the carrier board by using a pressure difference between a first predetermined pressure in the air bag and the working pressure of the processing chamber. Thereby, production quality of carrier board is significantly improved, as well as the cost for production of which is effectively reduced.
Laminated circuit board
Electronic devices to be integrated are formed on individual boards, the boards are laid to overlap each other in a predetermined relationship, and then through vias are formed at predetermined positions. With this, the electronic devices are electrically connected to each other, and function as an integrated device.
Method of forming semiconductor package transmission lines with micro-bump lines
Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.
Offset interposers for large-bottom packages and large-die package-on-package structures
An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
INSERTION LOSS REDUCTION AND INCREASED BONDING IN A CIRCUIT APPARATUS
A circuit apparatus includes a first circuit feature upon a first insulator and a second circuit feature upon the first insulator. The first circuit feature includes a planarized surface and the second circuit feature includes an irregular surface. The first circuit feature and the second circuit feature may be formed from patterning a conductive sheet that is upon the first insulator. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions thereof and is maintained in second regions thereof. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.
MASK STRUCTURE AND MANUFACTURING METHOD THEREOF
A mask structure and a manufacturing method of the mask structure are provided. The mask structure includes a transparent substrate, a patterned metal layer, and a plurality of microlens structures. The patterned metal layer is disposed on the transparent substrate and exposing a portion of the transparent substrate. The microlens structures are disposed on the transparent substrate exposed by a portion of the patterned metal layer and being in contact with the portion of the patterned metal layer.
PC board fluidic devices
PC board fluidic devices for performing a Polymerase Chain Reaction (PCR) are disclosed. The devices comprise a printed circuit board and a PCR chamber. The PCR chamber is a fluidic chamber and is located in, or is part of, the PC board. The PC board can include a coil trace heating element with a temperature sensor and controller.
Locking device with configurable electrical connector key and internal circuit board for electronic door locks
Locks, systems and methods of monitoring a lock, the lock having a hub with a slot rotatable by a handle to open and close a latchbolt. A locking member is moveable into and out of engagement with the hub slot to prevent and permit movement of the hub and latchbolt. A sensor on the lock, adjacent the hub and locking member, monitors a moving lock component. The sensor may sense the position of the locking member in or out of engagement with the hub slot. The sensor may be a reed switch actuated by a magnet on the moving lock component. The lock may further include a magnet mounted on the hub and the sensor may comprise a reed switch capable of being actuated by the magnet on the hub. The lock and system may include an external control unit having an alarm for controlling operation of the lock.
ELECTROCHROMIC WINDOW FABRICATION METHODS
Methods of manufacturing electrochromic windows are described. An electrochromic device is fabricated to substantially cover a glass sheet, for example float glass, and a cutting pattern is defined based on one or more low-defectivity areas in the device from which one or more electrochromic panes are cut. Laser scribes and/or bus bars may be added prior to cutting the panes or after. Edge deletion can also be performed prior to or after cutting the electrochromic panes from the glass sheet. Insulated glass units (IGUs) are fabricated from the electrochromic panes and optionally one or more of the panes of the IGU are strengthened.
Methods and Apparatus for Transmission Lines in Packages
Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.