Methods and systems for stacking multiple chips with high speed serializer/deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serializer/deserializer blocks, using the TVs.

A lead-cutting system, comprising: a rotation device configured to rotate a rotary table; a cutting device, being disposed on the rotary table, which is configured to cut leads of a lead component inserted into through-holes in a board; and a container, being disposed on the rotary table together with the cutting device, which contains leads cut by the cutting device.

Disclosed is a clinch mechanism for assembling a printed circuit board with electronic components that includes a drive shaft configured to move along a vertical axis, a stationary anvil configured to remain stationary during movement of the drive shaft, a cutter having a cutting tip, and a toggle configured to rotate about a toggle rotation axis that includes an involute gear shaped tooth configured to roll across an involute trapezoidal slot of the cutter in order to impart movement on the cutter relative to the stationary anvil. Movement of the drive shaft along the linear axis is configured to move the cutter relative to the stationary anvil, and to move the cutting tip across the stationary anvil to cut an electronic lead located between the cutting tip and the stationary anvil, and to rotate the toggle about the axis.

Methods and systems for stacking multiple chips with high speed serializer/deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads.

A substrate inspection apparatus may include: a communication circuit; a plurality of light sources; an image sensor; at least one memory; and at least one processor. The processor may be configured to: generate insertion state information indicating an insertion state of each of a plurality of pins included in each of a plurality of first connectors by using the pattern light reflected from the pin tail of each of the plurality of pins; detect at least one second connector having an insertion defect by using the insertion reference information and the insertion state information of each of the plurality of pins; generate a control signal for adjusting at least one first process parameter, based on insertion state information for the plurality of pins included in the at least one second connector; and control the communication circuit to transmit the control signal to the connector insertion apparatus.

An electronic component mounter is provided which easily detects penetrating portions. An electronic component mounter comprises a holding section configured to hold a board having a penetrating portion penetrating the board in a front-rear direction and into which a lead of an electronic component is inserted; a light section disposed on one face from among the front face and the rear face of the board when the board is held by the holding section and configured to irradiate a light beam, which is direct light or reflected light, on to the board; and a light receiving section disposed on the other face from among the front face and the rear face of the board when the board is held by the holding section and configured to receive the light beam via the penetrating portion.

A component chuck device moves a pusher member downward when negative pressure is supplied, and holds a posture of a component by causing the pusher member to abut with an upper face of the component that is gripped in a gripping mechanism. Then, the component chuck device releases gripping of the component when supply of negative pressure is stopped, and a lead of the component is inserted into a hole of a substrate while holding the posture of the component by moving the pusher member downward while remaining abutted with the upper face of the component.

An electronic package comprising a substrate, standoff substrate(s) and electronic components located within a clearance and/or one or more cavities. The substrate comprises substrate via(s) and/or substrate Redistribution Layer(s) and/or one or more cavities and/or substrate through hole(s). The standoff substrate(s) is coupled to said substrate. The standoff substrate(s) forms a clearance on the top and/or bottom surface of said substrate. The standoff substrate(s) comprises standoff substrate via(s) and/or standoff substrate Redistribution Layer(s). The standoff substrate via(s) and/or said standoff substrate Redistribution Layer(s) are coupled to said substrate Redistribution Layer(s) and/or said substrate via(s). The electronic components is coupled to said substrate and/or said at least one standoff substrate. The electronic components including a first electronic component and a second electronic component. The first electronic component is the same electronic component as compared to the second electronic component.

Methods and systems for stacking multiple chips with high speed serialiser/deserialiser blocks are presented. These methods make use of Through Silicon Via (TSV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serialiser/deserialiser blocks, using the TSVs.

A system comprising a die stack having at least a first die and a second die; one or more Redistribution Layer(s); one or more Through Silicon Via(s); one or more Serial I/O(s); one or more contact pad(s); and a substrate. The die stack is configured to communicate through said one or more Redistribution Layer(s) and said Through Silicon Via(s). The first die and/or said second die is/are configured to communicate through said one or more Redistribution Layer(s) and said Through Silicon Via(s). The one or more Serial I/O(s) is/are configured to communicate through said one or more Redistribution Layer(s) and said Through Silicon Via(s).