A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

The present invention provides a flexible circuit electrode array adapted for neural stimulation, comprising: a polymer base layer; metal traces deposited on the polymer base layer, including electrodes suitable to stimulate neural tissue; a polymer top layer deposited on the polymer base layer and the metal traces at least one tack opening. The present invention provides further a method of making a flexible circuit electrode array comprising depositing a polymer base layer; depositing metal on the polymer base layer; patterning the metal to form metal traces; depositing a polymer top layer on the polymer base layer and the metal traces; and preparing at least one tack opening.

A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

The subject technology provides a method and apparatus for performing dual track routing. A pair of signal traces is routed in between two rows of contacts and at least one of the signal traces is modified to satisfy a routing restriction. The modification of the signal trace includes three trace segments that deviate the signal trace away from the source of the routing restriction.

A sensor system can be configured to perform dielectric spectroscopy (DS). For example, the system can include a sensor configured to measure dielectric permittivity of a fluid in response to an RF input signal. Associated interface electronics can include a transmitter to drive the sensor with the RF input signal and a receiver to receive and process an RF output signal from the sensor in response to the RF input signal.

This disclosure provides a package substrate, a flip-chip package circuit, and their fabrication methods. The package substrate includes: a first wiring layer having a first dielectric material layer and a first metal wire protruding from the first dielectric material layer; a conductive pillar layer formed on the first wiring layer and including a molding compound layer, a second dielectric material layer formed on the molding compound layer, and a metal pillar connected to the first metal wire; a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the metal pillar; and a protection layer formed on the second wiring layer.

A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.

A method of manufacturing an electronic module includes providing a conductive strip and a dielectric material. The method includes coating the dielectric material and the conductive strip to form a layered structure having a conductive layer defined by the conductive strip and a dielectric layer defined by the dielectric material. The method includes applying a carrier strip to the layered structure. The method includes processing the conductive layer to form a circuit while the layered structure is on the carrier strip. The method includes removing the carrier strip from the layered structure. The method includes applying the layered structure with the circuit to an electronic module substrate.

A circuit apparatus includes at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.

The present invention relates to a method of manufacturing an antenna for a radio frequency (RFID) tag. A web of material is provided to at least one cutting station in which a first pattern is generated in the web of material. A further cutting may occur to create additional modifications in order to provide a microchip attachment location and to selectively tune an antenna for a particular end use application. The cutting may be performed by a laser, die cutting, stamping or combinations thereof.