A method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate, patterning the first and second semiconductor layers into a fin structure, forming a dummy gate structure across the fin structure, depositing gate spacers over sidewalls of the dummy gate structure, removing the dummy gate structure to form a recess, removing the first semiconductor layers, depositing an interfacial layer wrapping the second semiconductor layers, depositing a high-k dielectric layer over the interfacial layer and over the sidewalls of the gate spacers, depositing a first gate electrode over the high-k dielectric layer, recessing the first gate electrode and the high-k dielectric layer to expose a top portion of the sidewalls of the gate spacers, depositing a low-k dielectric layer over the recessed high-k dielectric layer, and depositing a second gate electrode over the first gate electrode.

A transistor and a manufacturing method. The transistor includes a semiconductor base substrate, an active structure, a dielectric structure, and a gate stack structure. The active structure is formed on the semiconductor base substrate. The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region. The channel region includes at least two nanostructures stacked in a thickness direction of the semiconductor base substrate. In the channel region, a bottom nanostructure has a greater width than other nanostructures. The dielectric structure is formed between the semiconductor base substrate and the active structure. The dielectric structure is in contact with the bottom nanostructure. The gate stack structure is formed on a surface of the bottom nanostructure not in contact with the dielectric structure, and the gate stack surrounds a periphery of the other nanostructures.

A method for manufacturing a gate-all-around TFET device. The method comprises: forming, on a substrate, a channel stack comprising channel layer(s) and sacrificial layer(s) that alternate with each other; forming, on the substrate, a dummy gate astride the channel stack; forming a first spacer at a surface of the dummy gate; etching the sacrificial layer(s) to form recesses on side surfaces of the channel stack; forming second spacers in the recesses, respectively; fabricating a source and a drain separately, where a region for fabricating the source is shielded by a dielectric material when fabricating the drain, and a region for fabricating the drain is shielded by another dielectric material when fabricating the source; etching the dummy gate and the sacrificial layer(s) to form a space for a surrounding gate; and fabricating a surrounding dielectric-metal gate in the space.

A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.

A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.

A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Provided is a semiconductor device including a lower pattern layer including a first semiconductor material; a first conductivity-type doped pattern layer disposed on the lower pattern layer and including a semiconductor material doped with a first conductivity-type impurity; a source/drain pattern disposed on the first conductivity-type doped pattern layer and including a semiconductor material doped with a second conductivity-type impurity different from the first conductivity-type impurity; a channel pattern including semiconductor patterns connected between the source/drain patterns, stacked apart from each other, and including a second semiconductor material different from the first semiconductor material; and a gate pattern disposed on the first conductivity-type doped pattern layer and between the source/drain patterns, and surrounding the channel pattern.

A semiconductor device includes: a substrate, an active pattern extending in a first horizontal direction on the substrate, a plurality of nanosheets spaced apart from each other and stacked in a vertical direction on the active pattern, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets, a source/drain region disposed on at least one side of the gate electrode on the active pattern, the source/drain region including a first layer doped with a metal, and a second layer disposed on the first layer, and an inner spacer disposed between the gate electrode and the first layer, between each of the plurality of nanosheets, the inner spacer in contact with the first layer, the inner spacer including a metal oxide formed by oxidizing the same material as the metal.

A semiconductor structure includes a stacked device structure having a first field-effect transistor having a first source/drain region, and a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor having a second source/drain region and a gate region having first sidewall spacers. The stacked device structure further includes a frontside source/drain contact disposed on a first portion of a sidewall and a top surface of the second source/drain region, a first metal via connected to the frontside source/drain contact and to a first backside power line, and second sidewall spacers disposed on a first portion of the first metal via. The first sidewall spacers comprise a first dielectric material and the second sidewall spacers comprise a second dielectric material different than the first dielectric material.

Forces applied to the channel regions of semiconductor slabs in a first direction relative to the semiconductor slab, can create strains in the crystal structure that improve carrier mobility to improve drive strength in the channel region. In a three-dimensional (3D) FET structure, a work function metal layer is provided on opposing faces of semiconductor slabs to cause a force to be exerted on the channel regions in a first direction corresponding to current flow. The force in the first direction is either tensile force or compressive force, depending on a FET type (N or P) employing the semiconductor slab, and is provided to create strain in a crystalline structure of the semiconductor slab to improve carrier mobility in the channel region. Increasing carrier mobility in the channel regions in a 3D FET structure increases drive strength of the 3D FET, which saves area in an integrated circuit.