According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.

A semiconductor device includes: a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode. In the semiconductor substrate, a body region, a pillar region, and a barrier region are formed. The pillar region has an n-type impurity, is formed on a lateral side of the body region, and extends along a depth from a top surface of the semiconductor substrate to a lower end of the body region. The barrier region has an n-type impurity and is formed on a lower side of the body region and the pillar region. The barrier region is formed on the lower side of the pillar region. An n-type impurity concentration distribution in a depth direction in the pillar region and the barrier region has a maximum value in the pillar region. The n-type impurity concentration distribution has a folding point on a side deeper than the maximum value.

A graphene optoelectronic detector is disclosed, which comprises: an insulating substrate with a graphene layer disposed thereon; a first electrode disposed on the graphene layer or between the graphene layer and the insulating substrate; and a second electrode disposed on the graphene layer or between the graphene layer and the insulating substrate, wherein there is a predetermined distance between the first electrode and the second electrode, and the first electrode and the second electrode are at different electrical potentials, wherein a high-drift carrier moving region is disposed between the first electrode and the second electrode, and a low-drift carrier moving region is disposed outside the high-drift carrier moving region. In addition, the present invention further provides a method for detecting photons and electromagnetic energy using the aforementioned graphene detector.

Disclosed is a technique capable of reducing loss at the time of switching in a diode. A diode disclosed in the present specification includes a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, an anode region made of a second conductivity type semiconductor, an anode electrode made of metal, a barrier region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a concentration higher than that of the drift region, and a pillar region formed so as to connect the barrier region to the anode electrode and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region. The pillar region and the anode are connected through a Schottky junction.

The present application provides a semiconductor device and a method for fabricating the same. The device includes a substrate with a first top surface, first and second gate electrodes within the substrate, a first barrier layer, and a second barrier layer over the first barrier layer and the first gate electrode. A gate capping layer is placed over the second gate electrode, and a cell contact structure is disposed on the first top surface. The second gate electrode is above the first gate electrode, wherein the first gate electrode consists of a first member surrounded by the first barrier layer and a second member extending toward the first top surface, protruding from the first barrier layer. The second gate electrode surrounds the second barrier layer and the second member of the first gate electrode.

An integrated circuit device includes: a rear insulating layer; a nanosheet stacked structure arranged on the rear insulating layer and including a plurality of nanosheets; a pair of source/drain regions positioned on sides of the nanosheet stacked structure in a first horizontal direction; a gate electrode extending in a second horizontal direction intersecting the first horizontal direction, on the nanosheet stacked structure; a contact plug connected to at least one of the pair of source/drain regions; a rear contact plug passing through the rear insulating layer and connected to at least one of the pair of source/drain regions; and a spacer layer including a contact spacer layer surrounding part of a side surface of the rear contact plug.

Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.

The present disclosure is directed to methods for forming source/drain (S/D) epitaxial structures with a hexagonal shape. The method includes forming a fin structure that includes a first portion and a second portion proximate to the first portion, forming a gate structure on the first portion of the fin structure, and recessing the second portion of the fin structure. The method further includes growing a S/D epitaxial structure on the recessed second portion of the fin structure, where growing the S/D epitaxial structure includes exposing the recessed second portion of the fin structure to a precursor and one or more reactant gases to form a portion of the S/D epitaxial structure. Growing the S/D epitaxial structure further includes exposing the portion of the S/D structure to an etching chemistry and exposing the portion of the S/D epitaxial structure to a hydrogen treatment to enhance growth of the S/D epitaxial structure.

A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si.