Gates having air gaps therein, and methods of fabrication thereof, are disclosed herein. An exemplary gate includes a gate electrode and a gate dielectric. A first air gap is between and/or separates a first sidewall of the gate electrode from the gate dielectric, and a second air gap is between and/or separates a second sidewall of the gate electrode from the gate dielectric. A dielectric cap may be disposed over the gate electrode, and the dielectric cap may wrap a top of the gate electrode. The dielectric cap may fill a top portion of the first air gap and a top portion of the second air gap. The gate may be disposed between a first epitaxial source/drain and a second epitaxial source/drain, and a width of the gate is about the same as a distance between the first epitaxial source/drain and the second epitaxial source/drain.

A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.

A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.

A method for manufacturing an ohmic contact for a HEMT device, comprising the steps of: forming a photoresist layer, on a semiconductor body comprising a heterostructure; forming, in the photoresist layer, an opening, through which a surface region of the semiconductor body is exposed at said heterostructure; etching the surface region of the semiconductor body using the photoresist layer as etching mask to form a trench in the heterostructure; depositing one or more metal layers in said trench and on the photoresist layer; and carrying out a process of lift-off of the photoresist layer.

A semiconductor device includes an isolation structure in a substrate. The semiconductor device further includes a gate structure over a first region of the substrate, wherein the isolation structure surrounds the first region, the gate structure comprising a first section and a second section. The semiconductor device further includes a conductive field plate over the substrate, the conductive field plate extending between the first section and the second section and overlapping an edge of the first region, wherein the conductive field plate comprises a dielectric layer having a variable thickness. The semiconductor device further includes a first well in the substrate, wherein the first well overlaps the edge of the first region, and the first well extends underneath the isolation structure, and the conductive field plate extends beyond an outer-most edge of the first well.

An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.

A method to transfer a layer of graphene from one substrate to another substrate is provided. The method includes providing a first layered structure including, from bottom to top, a copper foil, a layer of graphene, an adhesive layer and a carrier substrate. The copper foil is removed exposing a surface of the layer of graphene. Next, an oxide bonding enhancement dielectric layer is formed on the exposed surface of the layer of graphene. A second layered structure including a receiver substrate and a dielectric oxide layer is provided. Next, an exposed surface of the dielectric oxide layer is bonded to an exposed surface of the oxide bonding enhancement dielectric layer. The carrier substrate and the adhesive layer are removed exposing the layer of graphene.

Semiconductor devices comprising two-dimensional (2D) materials and methods of manufacture thereof are described. In an embodiment, a method for manufacturing a semiconductor device comprising 2D materials may include: epitaxially forming a first 2D material layer on a substrate; and epitaxially forming a second 2D material layer over the first 2D material layer, the first 2D material layer and the second 2D material layer differing in composition.

Provided herein are devices, systems, and methods of employing the same for the performance of bioinformatics analysis. The apparatuses and methods of the disclosure are directed in part to large scale graphene FET sensors, arrays, and integrated circuits employing the same for analyte measurements. The present GFET sensors, arrays, and integrated circuits may be fabricated using conventional CMOS processing techniques based on improved GFET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense GFET sensor based arrays. Improved fabrication techniques employing graphene as a reaction layer provide for rapid data acquisition from small sensors to large and dense arrays of sensors. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes, including DNA hybridization and/or sequencing reactions. Accordingly, GFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis within a gated reaction chamber of the GFET based sensor.