Patent classifications
H10F39/80377
Semiconductor device comprising an insulating layer including a void
A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.
Transistors having increased effective channel width
An image sensor includes a photodiode disposed in a semiconductor substrate having a first surface and a second surface opposite to the first surface. A floating diffusion is disposed in the semiconductor substrate. A transfer transistor is configured for coupling the photodiode to the floating diffusion. The transfer transistor includes a vertical transfer gate extending a first depth in a depthwise direction from the first surface into the semiconductor substrate. A transistor is coupled to the floating diffusion. The transistor includes: a planar gate disposed proximate to the first surface of the semiconductor substrate; and a plurality of vertical gate electrodes, each extending a respective depth into the semiconductor substrate from the planar gate in the depthwise direction. The respective depth of at least one of the plurality of vertical gate electrodes is the same as the first depth of the vertical transfer gate.
Image sensing device
An image sensing device includes a pixel array of a plurality of unit pixels arranged in a row direction and a column direction and including a first unit pixel that includes floating diffusion region configured to store photocharge generated within the first unit pixel in corresponding to incident light; a first gain conversion transistor connected to the first floating diffusion region; a first row booster block connected to the first gain conversion transistor and a second gain conversion transistor that is included in a second unit pixel adjacent to the first unit pixel in the row direction; and a first column booster block connected to the first gain conversion transistor and a third gain conversion transistor that is included in a third unit pixel adjacent to the first unit pixel in the column direction.
IMAGING DEVICE AND OPERATING METHOD THEREOF
An imaging device that has a high degree of freedom for exposure time and is capable of taking an image with little distortion is provided. In an n-th frame period where n is a natural number of two or more, a potential of a first charge accumulation portion is reset; the first charge accumulation portion is charged with a potential in accordance with an output of a photoelectric conversion element and simultaneously, imaging data in the (n1)-th frame that is output in accordance with a potential of a second charge accumulation portion is read; a potential of the second charge accumulation portion is reset; a potential of the first charge accumulation portion is transferred to the second charge accumulation portion, and a potential of the second charge accumulation portion is held. Through the steps, the degree of freedom for an exposure period is increased.
METHODS FOR CLOCKING AN IMAGE SENSOR
A method of clocking an image sensor which eliminates well bounce effects caused by global current flow in large image sensors during frame readout and line transfer is described. During charge transfer operations in which voltages are applied to VCCD gate contacts that are adjacent to the photodiodes, a compensating voltage may be applied to the lightshield that is associated with, and at least partially formed over the photodiode. Depending on polarity, the compensating lightshield pulse allows holes to locally flow from under the VCCD gates to the photodiode P+ pinning region or vice-versa, and in such a manner to eliminate the global flow of hole current. Lightshields may also be biased during electronic shuttering operations.
CMOS image sensors having a transfer gate electrode, and methods of fabricating CMOS image sensors having a transfer gate electrode
Complementary metal-oxide-semiconductor (CMOS) image sensors are provided. A CMOS image sensor includes a substrate including a pixel array and a peripheral circuit region, a photodiode and a floating diffusion region in the pixel array of the substrate, a transfer gate insulating layer and a transfer gate electrode on the substrate between the photodiode and the floating diffusion region, and a peripheral gate insulating layer and a peripheral gate electrode on the peripheral circuit region. The transfer gate electrode includes a first edge that is rounded to have a first radius of curvature, and the peripheral gate electrode includes a second edge that is rounded to have a second radius of curvature smaller than the first radius of curvature.
Solid-state imaging device, method for driving solid-state imaging device, and electronic apparatus
A solid-state imaging device, a method for driving a solid-state imaging device and an electronic apparatus are capable of reducing kTC noise of a LCG signal, preventing a drop in SNR at the conjunction point between a HCG signal and the LCG signal, and eventually achieving improved image quality. At a start of a reset period, first and second reset transistors are switched into a conduction state. During a predetermined first period after the reset period starts, the first reset line is kept connected to a reset potential. After the first period elapses, the second reset transistor is switched into a non-conduction state to switch the first reset line into a floating state, so that the first reset line has high impedance. After a second period elapses and when the reset period ends, the first reset transistor is switched into the non-conduction state.
Imaging device, manufacturing method thereof, and electronic device
An imaging device suitable for detecting infrared light is provided. The imaging device includes a first layer, a second layer, a third layer, and a fourth layer, which are stacked in this order. The first layer includes an infrared-light-transmitting filter. The second layer includes single crystal silicon. The third layer includes a device-formation layer. The fourth layer includes a support substrate. The second layer includes a photoelectric-conversion device whose light-absorption layer is the single crystal silicon. The third layer includes a transistor which includes a metal oxide in its channel formation region. The photoelectric-conversion device and the transistor are electrically connected. The photoelectric-conversion device receives light which has passed through the infrared-light-transmitting filter.
METHOD OF MAKING COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR IMAGE SENSOR
A method of making a pixel includes doping a workpiece to define a photosensitive device. The method further includes etching the workpiece to define a protrusion and a bulk, wherein the protrusion is above the bulk, and the photosensitive device is in both the protrusion and the bulk. The method further includes doping the protrusion to define a protrusion doping region in the protrusion. The method further includes forming an isolation structure in the protrusion surrounding the protrusion doping region.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.