A semiconductor device is provided. The semiconductor device includes a plurality of first semiconductor nanostructures formed over a substrate, and a first S/D structure formed on sidewall surfaces of the first semiconductor nanostructures. The semiconductor device includes a plurality of second semiconductor nanostructures formed over the substrate, and a second S/D structure formed on sidewall surfaces of the second semiconductor nanostructures. The semiconductor device includes an isolation structure formed between the first S/D structure and the second S/D structure, and the isolation structure has a first sidewall surface in direct contact with the first S/D structure and a second sidewall surface in direct contact with the second S/D structure.

An exemplary method includes forming an opening in an interlevel dielectric (ILD) layer. The opening in the ILD layer exposes a doped epitaxial layer. The method further includes performing an in-situ doping deposition process, an annealing process, and an etching process to form a doped semiconductor layer over the doped epitaxial layer. The doped semiconductor layer partially fills the opening. The method further includes forming a metal-comprising structure that fills a remainder of the opening. The metal-comprising structure is disposed over a top and sidewalls of the doped epitaxial layer. The doped semiconductor layer is disposed between the metal-comprising structure and the top of the doped epitaxial layer and between the metal-comprising structure and the sidewalls of the doped epitaxial layer. The in-situ deposition process may implement a temperature less than about 350 C. The doped epitaxial layer includes p-type dopant (e.g., boron), and the doped semiconductor layer includes gallium.

A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a gate electrode layer disposed over a substrate, a source/drain epitaxial feature disposed over the substrate, a first hard mask layer disposed over the gate electrode layer, and a contact etch stop layer (CESL) disposed over the source/drain epitaxial feature. The structure further includes a first interlayer dielectric (ILD) layer disposed on the CESL and a first treated portion of a second hard mask layer disposed on the CESL and the first ILD layer. A top surface of the first hard mask layer and a top surface of the first treated portion of the second mask layer are substantially coplanar. The structure further includes an etch stop layer disposed on the first hard mask layer and the first treated portion of the second mask layer.

A method includes forming a fin protruding over a substrate; forming a conformal oxide layer over an upper surface and along sidewalls of the fin; performing an anisotropic oxide deposition or an anisotropic plasma treatment to form a non-conformal oxide layer over the upper surface and along the sidewalls of the fin; and forming a gate electrode over the fin, the conformal oxide layer and the non-conformal oxide layer being between the fin and the gate electrode.

Neighboring gate-all-around integrated circuit structures having a conductive contact stressor between epitaxial source or drain regions are described. In an example, a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening conductive contact structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures. The intervening conductive contact structure imparts a stress to the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.

A semiconductor device include a substrate having a gate area and a contact area, a buried insulating layer formed over the substrate, a fin-type insulating pattern formed over the buried insulating layer and extending in a first horizontal direction, a lower metal layer covering an upper surface and side surfaces of the fin-type insulating pattern in the contact pattern, a channel layer covering an upper surface and side surfaces of the lower metal layer in the contact area and covering the upper surface and the side surfaces of the fin-type insulating pattern in the gate area, a gate pattern disposed over the channel layer in the gate area and extending in a second direction, and a source/drain contact pattern disposed over the channel layer in the contact area. The lower metal layer includes a Ti-based metal. The channel layer includes an oxide semiconductor material.

A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.