Semiconductor devices and methods of manufacture are presented. In embodiments a method of manufacturing the semiconductor device includes forming a fin from a plurality of semiconductor materials, depositing a dummy gate over the fin, depositing a plurality of spacers adjacent to the dummy gate, removing the dummy gate to form an opening adjacent to the plurality of spacers, widening the opening adjacent to a top surface of the plurality of spacers, after the widening, removing one of the plurality of semiconductor materials to form nanowires, and depositing a gate electrode around the nanowires.

An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.

Various transistors, such as field-effect transistors, and methods of fabricating the transistors are disclosed herein. An exemplary transistor includes a phosphorene-containing layer having a channel region, a source region, and a drain region defined therein. A passivation layer is disposed over the phosphorene-containing layer. A source contact and a drain contact extend through the passivation layer, such that the source contact and the drain contact are respectively coupled with the source region and the drain region. A gate stack is disposed over the channel region. In some embodiments, the gate stack includes a gate dielectric layer and a gate electrode layer, where the gate dielectric layer extends through the passivation layer and contacts the channel region. In some embodiments, the gate stack includes a gate electrode layer disposed over the passivation layer, and a portion of the passivation layer serves as a gate dielectric layer of the gate stack.

The application provides a thin film transistor, a method for manufacturing the thin film transistor, and a display panel, the thin film transistor includes a metal electrode, and a step of forming the metal electrode includes: forming a first material layer on a substrate; performing a pattering process on the first material layer to form a groove pattern in the first material layer such that the groove pattern matches with a pattern of the metal electrode to be formed; forming the metal electrode in the groove pattern such that a gap is formed between an edge of the metal electrode and an edge of the groove pattern; forming a protection pattern on the substrate formed with the metal electrode such that the protection pattern covers the metal electrode and its edge. In the application, the protection pattern is formed on the resultant metal electrode and can effectively protect conductive metal.

A nanowire structure includes successive crystalline nanowire segments formed over a semiconductor substrate. A first crystalline segment formed directly on the semiconductor substrate provides electrical isolation between the substrate and the second crystalline segment. Second and fourth crystalline segments are each formed from a p-type or an n-type semiconductor material, while the third crystalline segment is formed from a semiconductor material that is oppositely doped with respect to the second and fourth crystalline segments.

In an aspect of the present invention, a graphene field-effect transistor (GFET) structure is formed. The GFET structure comprises a wider portion and a narrow extension portion extending from the wider portion that includes one or more graphene layers edge contacted to source and drain contacts, wherein the source and drain contacts are self-aligned to the one or more graphene layers.

Embodiments of the present invention provide a thin film transistor, method for fabricating the thin film transistor and display apparatus. The method includes steps of: forming an active layer pattern which has a mobility greater than a predetermined threshold from an active layer material; and performing ion implantation on the active layer pattern. The energy of a compound bond formed from the implanted ions is greater than that of a compound bond formed from ions in the active layer material, thereby reducing the chance of vacancy formation and reducing the carrier concentration. Therefore, the mobility of the active layer surface is reduced, the leakage current is reduced, the threshold voltage is adjusted to shift toward positive direction and performance of the thin film transistor is improved.

Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Beneath each gate, a single gap fill dielectric layer extends vertically from a lower surface of the gate, at least partially separating the gate from the underlying global bit line. Between horizontally adjacent pillars, this same dielectric layer extends from its same lower level beneath the gates vertically to a level of the upper source/drain region.

The present invention discloses a method for manufacturing a thin-film transistor, comprising the steps of: forming a semiconductor active layer, and a doped semiconductor active layer; forming a source-drain metal layer; forming a channel region; and implanting ions for lowering the TFT leakage current into the surface of the semiconductor active layer in the channel region via ion implantation after forming the channel region. The invention further relates to a thin-film transistor, a TFT array substrate and a display device. The invention has the following beneficial effects: by implanting ions for lowering the TFT leakage current into the channel region, the electrical performance of a TFT may be improved, and the thickness of a semiconductor active layer in a channel region may be changed controllably.

Embodiments are directed to forming a structure comprising at least one fin, a gate, and a spacer, applying an annealing process to the structure to create a gap between the at least one fin and the spacer, and growing an epitaxial semiconductor layer in the gap between the spacer and the at least one fin.