Thin film transistor, method for fabricating the same and display apparatus

Abstract

Embodiments of the present invention provide a thin film transistor, method for fabricating the thin film transistor and display apparatus. The method includes steps of: forming an active layer pattern which has a mobility greater than a predetermined threshold from an active layer material; and performing ion implantation on the active layer pattern. The energy of a compound bond formed from the implanted ions is greater than that of a compound bond formed from ions in the active layer material, thereby reducing the chance of vacancy formation and reducing the carrier concentration. Therefore, the mobility of the active layer surface is reduced, the leakage current is reduced, the threshold voltage is adjusted to shift toward positive direction and performance of the thin film transistor is improved.

Claims

1. A method for fabricating a thin film transistor, comprising: forming an active layer pattern from zinc oxynitride; and implanting Ga or Al ions into a top portion of a channel region of the active layer pattern so as to convert the channel region of the active layer pattern to a top layer of zinc oxynitride doped with Ga or Al ions and a bottom layer of zinc oxynitride, such that in the thin film transistor, a mobility of the top layer is less than a mobility of the bottom layer, wherein before the implanting, the method further comprises: forming an etch stop layer pattern on the active layer pattern, and forming a source/drain pattern on both the etch stop layer pattern and the active layer pattern.

2. The method according to claim 1, wherein before the implanting, the method further comprises: forming a protection layer on both the etch stop layer pattern and the source/drain pattern.

3. The method according to claim 2, wherein the protection layer is a laminated layer of SiOx and SiNx.

4. The method according to claim 1, wherein before the forming the active layer pattern, the method further comprises: forming a gate pattern on a substrate; and forming a gate insulating layer on both the gate pattern and the substrate, wherein the active layer pattern is formed on the gate insulating layer.

5. The method according to claim 2, wherein before the forming the active layer pattern, the method further comprises: forming a gate pattern on a substrate; and forming a gate insulating layer on both the gate pattern and the substrate, wherein the active layer pattern is formed on the gate insulating layer.

6. The method according to claim 3, wherein before the forming the active layer pattern, the method further comprises: forming a gate pattern on a substrate; and forming a gate insulating layer on both the gate pattern and the substrate, wherein the active layer pattern is formed on the gate insulating layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1a is a structural schematic view of a thin film transistor in which the gate pattern is formed during the fabricating process of the thin film transistor according to an embodiment of the present invention;

(2) FIG. 1b is a structural schematic view of a thin film transistor in which the gate insulating layer is formed during the fabricating process of the thin film transistor according to an embodiment of the present invention;

(3) FIG. 1c is a structural schematic view of a thin film transistor in which the active layer pattern is formed during the fabricating process of the thin film transistor according to an embodiment of the present invention;

(4) FIG. 1d is a structural schematic view of a thin film transistor in which the etch stop layer pattern is formed during the fabricating process of the thin film transistor according to an embodiment of the present invention;

(5) FIG. 1e is a structural schematic view of a thin film transistor in which the source/drain pattern is formed during the fabricating process of the thin film transistor according to an embodiment of the present invention;

(6) FIG. 1f is a structural schematic view of a thin film transistor in which the protection layer is formed during the fabricating process of the thin film transistor according to an embodiment of the present invention;

(7) FIG. 1g is a schematic view showing performing ion implantation during the fabricating process of the thin film transistor according to an embodiment of the present invention;

(8) FIG. 1h is a structural schematic view of a thin film transistor according to an embodiment of the present invention.

DETAILED DESCRIPTION

(9) In order to make objects, technical solutions and advantages of the embodiments of the invention apparent, the technical solutions of the embodiment will be described clearly and fully in connection with the drawings related to the embodiments of the invention. It is obvious that the described embodiments are just a part but not all of the embodiments of the invention. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the invention.

(10) At least one embodiment of the present invention provides a thin film transistor, a method for fabricating the thin film transistor and a display apparatus. According to the method for fabricating the thin film transistor provided by an embodiment of the present invention, when the mobility of the active layer material is greater than a predetermined threshold, in order to avoid large leakage current caused by a high mobility of the active layer, ion implantation is performed on the active layer to increase energy of the ionic bond of the active layer surface, thus reducing the chance of vacancy formation and reducing the carrier concentration. Therefore, the mobility of the active layer surface is reduced, the leakage current is reduced, threshold voltage is adjusted to shift toward positive direction and performance of the thin film transistor is improved.

(11) At least one embodiment of the present invention provides a method for fabricating a thin film transistor, comprising the following steps.

(12) Step S101: forming an active layer pattern from an active layer material, where the mobility of the active layer is greater than a predetermined threshold. For example, the active layer material having mobility greater than the predetermined threshold is first deposited, and then etched by using a mask so as to obtain the active layer pattern.

(13) Step S102: performing ion implantation on the active layer pattern. The energy of the compound bond formed from the implanted ions is greater than that of the compound bond formed from the ions in the active layer material.

(14) There are various methods to perform ion implantation, for example, the ion beam generated from ion sources is introduced into the target chamber through slits and then implanted into the target sheet. It is contemplated that those skilled in the art may perform ion implantation in other manners.

(15) After performing ion implantation on the active layer pattern, the surface mobility of the active layer pattern is reduced, while the mobility under the surface is still high. As such, the leakage current is reduced, the threshold voltage is adjusted to shift toward positive direction, and the performance of thin film transistor is improved.

(16) Typically, when the mobility is greater than about 30 cm.sup.2/Vs, it is considered to be a high mobility, thus, the ion implantation on the active layer pattern is necessary. When the energy of the compound bond formed from the implanted ions is greater than that of the compound bond formed from ions in the active layer material, both vacancy and carrier concentration in the active layer material can be reduced and thus the surface mobility of the active layer pattern is reduced.

(17) For example, when zinc oxynitride is used as the active layer material, mobility of the zinc oxynitride is about 100 cm.sup.2/Vs. Positions provided for the carriers, i.e., free carriers, in the zinc oxynitride, are nitrogen vacancies. Since both of energy of NGa (NGa bond) and energy of NAl (NAl bond) are higher than that of NZn (NZn bond), it is more difficult to form nitrogen vacancy in zinc oxynitride by using Ga or Al as dopant, and thus mobility of the zinc oxynitride is reduced.

(18) Alternatively, when IGZO (indium gallium zinc oxide) or ITZO (indium tin zinc oxide) is used as the active layer material, position provided for the carriers is oxygen vacancy. Since both of energy of OGa. (OGa bond) and energy of OAl (OAl bond) are higher than that of OZn (OZn bond), it is possible to use Ga or Al as dopant and reduce mobility of the IGZO or ITZO.

(19) In order to prevent the surface of the active layer pattern from being damaged during ion implantation, after forming the active layer pattern, an etch stop layer pattern is first formed on the active layer pattern, then a source/drain pattern is formed on both the etch stop layer pattern and the active layer pattern, finally, the ion implantation is performed on the active layer. Since the energy of the implanted ions is higher, the ions may pass through the etch stop layer pattern and reach the surface of the active layer pattern so as to achieve ion implantation.

(20) In this case, before step S102, the method further comprises: forming an etch stop layer pattern on the active layer pattern; and forming a source/drain pattern on both the etch stop layer pattern and the active layer pattern.

(21) Further, in order to prevent performance of the TFT from being impacted by the ion implantation, before performing ion implantation on the active layer, the method further comprises forming a protection layer on both the etch stop layer pattern and the source/drain pattern.

(22) Combination of SiOx and SiNx may be used as the protection layer. Likewise, since the energy of the implanted ions is higher, the ions may pass through the protection layer and the etch stop layer pattern, and reach the surface of the active layer pattern so as to achieve ion implantation. Ion bombardment on the surface of the active layer pattern during the ion implantation is also prevented.

(23) As an example, a gate electrode and a gate insulating layer are further disposed under the active layer pattern. In this case, before forming an active layer from an active layer material, step S101 further comprises: forming a gate pattern on a substrate; and forming a gate insulating layer on both the gate pattern and the substrate.

(24) In this case, the step of forming an active layer pattern having mobility greater than predetermined threshold from an active layer material is replaced with the step of forming an active layer pattern on the gate insulating layer from an active layer material having mobility greater than predetermined threshold.

(25) For example, a method for fabricating a thin film transistor provided by an embodiment of the present invention comprises the following steps.

(26) Step S201: forming a gate pattern on the substrate. Gate material may be deposited by magnetron sputtering method, and then patterning is performed on the gate material. Patterning of the gate may be achieved by exposure, development, etching, and lift-off processes. For example, the gate material may be metals such as Mo, Al and so on. The thin film transistor after forming the gate pattern is illustrated in FIG. 1a.

(27) Step S202: forming a gate insulating layer on both the gate pattern and the substrate. The gate insulating layer is a single layer or multilayer of SiOx and/or SiNx. The thin film transistor after forming the gate insulating layer is illustrated in FIG. 1b.

(28) Step S203: forming an active layer pattern on the gate insulating layer from an active layer material. Zinc oxynitride is deposited on the gate insulating layer and patterned to form the active layer pattern. The thin film transistor after forming the active layer pattern is illustrated in FIG. 1c.

(29) Step S204: forming an etch stop layer pattern on the active layer pattern. The etch stop layer material is deposited on the active layer pattern and patterned. The thin film transistor after forming the etch stop layer pattern is illustrated in FIG. 1d.

(30) Step S205: forming a source/drain pattern on both the etch stop layer pattern and active layer pattern. Source/drain material is deposited and patterned. The thin film transistor after forming the source/drain pattern is illustrated in FIG. 1e.

(31) Step S206: forming a protection layer on both the etch stop layer pattern and source/drain pattern. The protection layer is a combination of SiOx and SiNx. The thin film transistor after forming the protection layer is illustrated in FIG. 1f.

(32) Step S207: performing ion implantation on the active layer pattern as illustrated in FIG. 1g.

(33) Since the energy of the implanted ions is higher, the ions is implanted into the surface of the active layer pattern through the protection layer and etch stop layer, so that the active layer comprises a top layer doped with Ga ion or Al ion and a bottom layer of zinc oxynitride. The thin film transistor after ion implantation is illustrated in FIG. 1h.

(34) At least one embodiment of the present invention provides a thin film transistor comprising an active layer pattern, where the mobility of the active layer material is greater than a predetermined threshold, the surface of the active layer pattern is doped with predetermined ions, such that the energy of the compound bond formed from the predetermined ions is greater than that of the compound bond formed from ions in the active layer material.

(35) At least one embodiment of the present invention further provides a thin film transistor fabricated by the method for fabricating the thin film transistor according to embodiments of the present invention.

(36) At least one embodiment of the present invention further provides a display apparatus comprising the thin film transistor provided by embodiments of the present invention.

(37) At least one embodiment of the present invention provides a thin film transistor, a method for fabricating the thin film transistor and a display apparatus. When the mobility of the active layer material is greater than a predetermined threshold, in order to avoid large leakage current caused by a high mobility of the active layer, ion implantation is performed on the active layer to increase energy of the ionic bond of the active layer surface, thus reducing the chance of vacancy formation and reducing the carrier concentration. Therefore, the surface mobility of the active layer is reduced, leakage current is reduced, threshold voltage is adjusted to shift toward positive direction and performance of the thin film transistor is improved.

(38) It is obvious that various variations and modifications can be made to embodiments of the present invention without departing spirit and scope of the present invention. If those variations and modifications are within the protection scope defined by the claims and equivalent technique, the present invention is intended to include those variations and modifications.

(39) The present application claims priority from Chinese Application Serial Number 201310473410.3 filed on Oct. 11, 2013, the disclosure of which is hereby incorporated by reference herein in its entirety.