A method for fabricating a semiconductor device may include: preparing a semiconductor substrate including a doping region; performing tilt implantation using a first additional dopant to form an amorphous region in the doping region; doping a second additional dopant in the amorphous region; forming a metal layer on the doped amorphous region; and reacting the doped amorphous region with the metal layer to form metal silicide.

A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.

Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.

A method for manufacturing a semiconductor element includes forming a first region in a semiconductor region by ion-implanting impurities using a first mask; forming an interconnect including a gate portion extending in a first direction over the first region; and forming a source/drain region by ion-implanting impurities into a second region. A gate threshold voltage of the semiconductor element has first to third correlations dependent respectively on distances between an inner wall of the first mask and an outer edge of the second region, between the gate portion and the outer edge of the second region and between the outer edge of the second portion and a portion of the interconnect other than the gate portion. At least one of the distances is determined based on the first to third correlations to obtain a prescribed gate threshold voltage of the semiconductor element.

In order to form a light receiving element having high reliability and a MOS transistor together on the same silicon substrate, after forming a gate electrode of the MOS transistor, a gate oxide film in a light receiving element forming region is removed. Then, a thermal oxide film is newly formed in the light receiving element forming region, and ion implantation is performed in the light receiving element forming region through the thermal oxide film such that a shallow pn junction is formed.

A semiconductor device includes a substrate, a gate dielectric layer on the substrate, and a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line, a wetting layer, a metal diffusion blocking layer, and a work function layer. The wetting layer is in contact with a sidewall and a bottom surface of the metal filling line. The metal diffusion blocking layer is in contact with the wetting layer and covers the sidewall and the bottom surface of the metal filling line with the wetting layer therebetween. The work function layer covers the sidewall and the bottom surface of the metal filling line with the wetting layer and the metal diffusion blocking layer therebetween.

The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the transistors, defining and forming well regions for all of the transistors, forming a gate oxide layer in the well regions for all of the transistor, forming gates for all of the transistors over the gate oxide layer, implanting a dopant to form lightly-doped drain regions for all of the transistors, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions, forming gate spacers at sides of the gates of all of the transistors, and implanting a dopant to form sources and drains for all of the transistors, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.

A method of forming a semiconductor device is provided. At least two shallow trenches are formed in a substrate. An insulating layer is formed on surfaces of the substrate and the shallow trenches. A conductive layer is formed on the substrate between the shallow trenches. At least one spacer is formed on a sidewall of the conductive layer, wherein the spacer fills up each shallow trench.

An integrated circuit (IC) using high- metal gate (HKMG) technology with an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate, and the control transistor further comprises a charge trapping layer underlying the control gate. The logic gate and one or both of the control and select gates are metal and arranged within respective high dielectric layers. A high--last method for manufacturing the IC is also provided.