A transistor that can be miniaturized is provided. The semiconductor device includes an oxide semiconductor layer, first to fourth conductive layers, and first to fourth insulating layers. Over the first conductive layer including a depressed portion, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer which include a first opening portion overlapping with the depressed portion are provided in this order. The third insulating layer is in contact with at least the side surface of the second conductive layer in the first opening portion. The oxide semiconductor layer is in contact with the top surface of the third conductive layer and the bottom and side surfaces of the depressed portion, and is in contact with the third insulating layer in the first opening portion. The fourth insulating layer is on an inner side of the oxide semiconductor layer in the first opening portion. The fourth conductive layer is on an inner side of the fourth insulating layer in the first opening portion. In a cross-sectional view, the oxide semiconductor layer includes a region overlapping with the second conductive layer with the third insulating layer therebetween and overlapping with the fourth conductive layer with the fourth insulating layer therebetween.

A semiconductor device including an oxide semiconductor layer which is formed over a substrate and includes indium is provided. The oxide semiconductor layer is formed in parallel or substantially in parallel with a surface of the substrate. The oxide semiconductor layer includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a formation surface of the oxide semiconductor layer to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the formation surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the formation surface are observed in each of the first region, the second region, and the third region.

A display device that is suitable for increasing in size is achieved. Three or more source lines are provided for each pixel column. Video signals having the same polarity are input to adjacent source lines during one frame period. Dot inversion driving is used to reduce a flicker, crosstalk, or the like.

A metal oxide film containing a crystal part is provided. Alternatively, a metal oxide film with highly stable physical properties is provided. Alternatively, a metal oxide film with improved electrical characteristics is provided. Alternatively, a metal oxide film with which field-effect mobility can be increased is provided. A metal oxide film including In, M (M is Al, Ga, Y, or Sn), and Zn includes a first crystal part and a second crystal part; the first crystal part has c-axis alignment; the second crystal part has no c-axis alignment; and the existing proportion of the second crystal part is higher than the existing proportion of the first crystal part.

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/m (110.sup.18 A/m) or less. Therefore, the drive capability of the semiconductor device can be improved.

A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.

A structure that includes a circuit for controlling the safe operation of a secondary battery but can overcome space limitations owing to miniaturization of the housing is provided. A charge control circuit is provided over a flexible substrate and bonded to an external surface of the secondary battery. The charge control circuit is electrically connected to at least one of two terminals of the secondary battery and controls charging. To prevent overcharge, both an output transistor of a charging circuit and a blocking switch are brought into off state substantially concurrently. Blocking two paths which connect to the battery can quickly stop charging when overcharge is detected and reduce damage to the battery owing to the overcharge.

An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

Provided are a display device and a method for manufacturing the same. The display device includes: a connection source electrode and a connection drain electrode connected to a first source electrode a the first drain electrode, respectively by penetrating an isolation insulating layer and a second interlayer dielectric layer to enhance a characteristic of an element and reliability of the display device.