The present application provides a semiconductor device and a method for fabricating the same. The device includes a substrate with a first top surface, first and second gate electrodes within the substrate, a first barrier layer, and a second barrier layer over the first barrier layer and the first gate electrode. A gate capping layer is placed over the second gate electrode, and a cell contact structure is disposed on the first top surface. The second gate electrode is above the first gate electrode, wherein the first gate electrode consists of a first member surrounded by the first barrier layer and a second member extending toward the first top surface, protruding from the first barrier layer. The second gate electrode surrounds the second barrier layer and the second member of the first gate electrode.

A semiconductor integrated circuit device may include a standard cell region on a surface of a substrate and a first active region on the surface of the substrate in the standard cell region, wherein the first active region has a length in a first direction. A second active region may be on the surface of the substrate in the standard cell region, the second active region may have a length in the first direction, the length of the second active region may be greater than the length of the first active region, and an axis in a second direction may intersect centers of the first and second active regions so that the first and second active regions are symmetric about the axis in the second direction. A first gate electrode may extend across the first active region in the first direction, and a second gate electrode may extend across the second active region in the first direction.

According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.

A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT (100) are provided. The SiC BJT comprises an emitter region (150), a base region (140) and a collector region (120). The collector region is arranged on a substrate (110) having an off-axis orientation of about 8 degrees or lower. A defect termination layer (DTL, 130) for terminating dislocations originating from the substrate is arranged between the substrate and the collector region. The collector region includes a zone (125) in which the life time of the minority charge carriers is shorter than in the base region. The present invention is advantageous in terms of improved stability of the SiC BJTs.

The present disclosure relates to a semiconductor device and a method of manufacturing semiconductor device. The present disclosure relates particularly to MOSFET transistors. A semiconductor device according to the disclosure including: a first-conductivity-type substrate, a first-conductivity-type epitaxy layer including a JFET region and a second-conductivity-type shield region, two well regions including two source regions, gate oxide including a gate, a drain adjacent to the first-conductivity-type substrate, the first-conductivity-type substrate is adjacent to the first-conductivity-type epitaxy layer, the two well regions are adjacent to the first-conductivity-type epitaxy layer, the JFET region is located between the two well regions, the source contact region is the outermost layer and is adjacent to the two source regions, and the gate oxide is adjacent to the two well regions, the two source regions, and the JFET region.

Semiconductor devices configured to achieve a high withstand voltage are disclosed. In one example, a semiconductor device includes an SJ layer extending in a first direction and configured by alternately arraying semiconductor regions of a first conductivity type and semiconductor regions of a second conductivity type in a second direction orthogonal to the first direction. A first drain layer of the first conductivity type is electrically connected to the SJ layer on a first end side in the first direction, a channel layer of the second conductivity type is provided on the SJ layer on a second end side in the first direction, a first source layer of the first conductivity type is provided on the channel layer, and a first gate electrode is provided on a side of the channel layer and the first source layer in the first direction with a first insulating layer interposed therebetween.

A semiconductor structure includes a substrate including a first region, a second region and a third region located between the first region and the second region; a channel structure formed on the substrate; and a first P-type buried layer located in the third region. The first P-type buried layer extends along a direction parallel to a channel width. In the semiconductor structure, the first P-type buried layer is disposed in the substrate, and is configured to deplete the two-dimensional electron gas in the channel structure so as to achieve an enhancement-mode semiconductor structure. With this disposure, the problems of gate leakage, the electric field concentration effect of the gate close to the edge of the drain and the like are avoided, and tedious steps of manufacturing a P-type semiconductor layer above a channel structure in conventional method is avoided, which simplifies the manufacturing method, and effectively improves the production efficiency.

A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.

Device scaling has increased the device density of integrated circuits (ICs) and reduced the cost of circuits. Today development of new device structures, use of new materials and complex process steps are implemented to continue scaling of the semiconductor devices. The added manufacturing steps and complexity have increased cost of ICs directly impacting the implementation of IoT devices that need low cost and high yields to be successful. ALEFT-ISD-LTSEE is a device that reduces the cost while improving device performance. ALEFT-ISD-LTSEE is suitable for continued scaling of gate and channel lengths while reducing impact of random threshold variation due to discrete dopants in and around the channel by elimination of implants and high temperature processing. By creating a flat field profile at the gate by use of low temperature epitaxy as source/drain extension, the short channel effects, and the impact of line edge variations of the gate are also reduced.

A method of fabricating a semiconductor device includes the following steps. A substrate is provided. A semiconductor channel layer is formed on the substrate. A semiconductor barrier layer is formed on the semiconductor channel layer. An etching process is performed to expose a portion of the semiconductor channel layer. A dielectric layer is formed to cover the semiconductor barrier layer and the exposed semiconductor channel layer. A first electrode is formed after forming the dielectric layer, where the first electrode includes a body portion and a vertical extension portion, the body portion is electrically connected to the semiconductor barrier layer, and a bottom surface of the vertical extension portion is lower than a top surface of the semiconductor channel layer.