A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin base on a substrate, epitaxially growing a S/D region on the fin base, forming a contact opening on the S/D region, forming a semiconductor nitride layer on a sidewall of the contact opening, performing a densification process on the semiconductor nitride layer to form a densified semiconductor nitride layer, forming a silicide layer on an exposed surface of the S/D region in the contact opening, forming a contact plug in the contact opening, and forming a via structure in the contact plug.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a trench isolation between a first source/drain region of a first transistor and a second source/drain region of a second transistor, wherein the trench isolation includes an upper portion and a lower portion; the lower portion has a first lower sidewall and a second lower sidewall that intersects with the first lower sidewall to form a pointy bottom of the trench isolation; a first lower conformal liner at the first lower sidewall and a second lower conformal liner at the second lower sidewall; and the first and second lower conformal liners pinch off at the pointy bottom. A method of forming the same is also provided.

A semiconductor device includes a fin-type active region that extends in length in a first horizontal direction on a substrate, a horizontal semiconductor layer on the fin-type active region, a seed layer on the fin-type active region and in contact with the horizontal semiconductor layer, a gate line that surrounds the horizontal semiconductor layer and the seed layer, on the fin-type active region, and that extends in length in a second horizontal direction that intersects the first horizontal direction, and a pair of vertical semiconductor layers respectively on first and second sides of the horizontal semiconductor layer in the first horizontal direction, on the fin-type active region, with the horizontal semiconductor layer therebetween, wherein an inner wall of each of the first and second vertical semiconductor layers contacts the horizontal semiconductor layer, and upper or lower surfaces of the vertical semiconductor layers contact the seed layer.

A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including semiconductor patterns vertically stacked to be spaced apart from each other, a gate electrode on the plurality of semiconductor patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the gate contact, the first metal layer including a first conductive via and a first interconnection pattern on the first conductive via, a second metal layer on the first metal layer, the second metal layer including a second conductive via and a second interconnection pattern on the second conductive via, and a diffusion prevention pattern between the first interconnection pattern and the second conductive via. A level of a bottom surface of the diffusion prevention pattern may be lower than a level of the topmost surface of the first interconnection pattern.

Provided are a display device and a method for manufacturing the same. The display device includes: a connection source electrode and a connection drain electrode connected to a first source electrode a the first drain electrode, respectively by penetrating an isolation insulating layer and a second interlayer dielectric layer to enhance a characteristic of an element and reliability of the display device.

A thin film transistor is provided. The thin film transistor comprises a gate electrode, an InZnSn oxide (IZTO) channel layer that overlaps the top or bottom of the gate electrode and has a spinel single-phase crystalline, a gate insulating layer disposed between the gate electrode and the IZTO channel layer, and source and drain electrodes respectively connected to both ends of the IZTO channel layer.

A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.

A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

A semiconductor device may include first and second fin-shaped patterns on a substrate, that extend in a first direction, and are spaced apart from each other in a second direction. A first epitaxial pattern may be on the first fin-shaped pattern, and a second epitaxial pattern may be on the second fin-shaped pattern. A field insulating layer may be on the substrate, and may cover a sidewall of the first fin-shaped pattern, a sidewall of the second fin-shaped pattern, a part of a sidewall of the first epitaxial pattern, and a part of a sidewall of the second epitaxial pattern. The top surface of the field insulating layer may be higher than the bottom surface of the first epitaxial pattern and the bottom surface of the second epitaxial pattern.