In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a well region, a drain region and a source region disposed in the well region, a gate electrode disposed above the well region, a thin gate insulating layer and a thick gate insulating layer disposed under the gate electrode, the thick gate insulating layer being disclosed closer to the drain region than the thin gate insulating layer, and an extended drain junction region disposed below the gate electrode.

A MOS transistor comprises a substrate of a first conductivity, a first region of the first conductivity formed over the substrate, a second region of the first conductivity formed in the first region, a first drain/source region of a second conductivity formed in the second region, a second drain/source region of the second conductivity and a body contact region of the first conductivity, wherein the body contact region and the first drain/source region are formed in an alternating manner from a top view.

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region.

A semiconductor device includes a semiconductor substrate, and a P-well and an N-type drift region disposed in the semiconductor substrate. The P-well includes a lower well region and an upper well region disposed above the lower well region. The lower well region includes a first surface that is near the N-type drift region, and the upper well region includes a second surface that is near the N-type drift region. A distance from the first surface of the lower well region to the N-type drift region is greater than a distance from the second surface of the upper well region to the N-type drift region.

In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

A semiconductor device includes a split-gate lateral extended drain MOS transistor, which includes a first gate and a second gate laterally adjacent to the first gate. The first gate is laterally separated from the second gate by a gap of 10 nanometers to 250 nanometers. The first gate extends at least partially over the body, and the second gate extends at least partially over a drain drift region. The drain drift region abuts the body at a top surface of the substrate. A boundary between the drain drift region and the body at the top surface of the substrate is located under at least one of the first gate, the second gate and the gap between the first gate and the second gate. The second gate may be coupled to a gate bias voltage node or a gate signal node.

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate, and having a conductivity type in common with the doped isolation barrier and the drain region. The depleted well region is positioned between the doped isolation barrier and the drain region to electrically couple the doped isolation barrier and the drain region such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the drain region.

A semiconductor device with improved characteristics is provided. The semiconductor device includes a LDMOS, a source plug electrically coupled to a source region of the LDMOS, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the LDMOS, and a drain wiring disposed over the drain plug. The structure of the source plug of the semiconductor device is devised. The semiconductor device is structured such that the drain plug is linearly disposed to extend in a direction Y, and the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the direction Y. In this way, the separation of the source plug decreases an opposed area between the source plug and the drain plug, and can thus decrease the parasitic capacitance therebetween.

A semiconductor device has a substrate and gate structure over the substrate. A source region is formed in the substrate adjacent to the gate structure. A drain region in the substrate adjacent to the gate structure opposite the source region. An interconnect structure is formed over the substrate by forming a conductive plane electrically connected to the source region, and forming a conductive layer within openings of the conductive plane and electrically connected to the drain region. The interconnect structure can be formed as stacked conductive layers laid out in alternating strips. The conductive plane extends under a gate terminal of the semiconductor device. An insulating layer is formed over the substrate and a field plate is formed in the insulating layer. The field plate is electrically connected the source terminal. A stress relief layer is formed over a surface of the substrate opposite the gate structure.