Provided are a semiconductor device and a method of forming the same. The semiconductor device includes an active region defined by an isolation layer. A source region portion, a drain region portion and a channel region are located in the active region. The channel region includes a first portion located close to the source region portion and a second portion having a higher threshold voltage than the first portion.

Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes an array having at least one first region and at least one second region. The at least one first region includes at least one first device oriented in a first direction. The at least one second region includes at least one second device oriented in a second direction. The second direction is different than the first direction.

A lateral double diffused metal oxide semiconductor device, includes: a P-type substrate, an epitaxial layer, a P-type high voltage well, a P-type body region, an N-type well, an isolation oxide region, a drift oxide region, a gate, an N-type contact region, a P-type contact region, a top source, a bottom source, and an N-type drain. The P-type body region is between and connects the P-type high voltage well and the surface of the epitaxial layer. The P-type body region includes a peak concentration region, which is beneath and in direct contact the surface of the epitaxial layer, wherein the peak concentration region has a highest P-type impurity concentration in the P-type body region. The P-type impurity concentration of the P-type body region is higher than a predetermined threshold to suppress a parasitic bipolar transistor such that it does not turn ON.

Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region, which is separated from the isolation structure by a portion of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.

Semiconductor devices include a semiconductor substrate containing a source region and a drain region, a gate structure supported by the semiconductor substrate between the source region and the drain region, a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region including dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range, and a well region in the semiconductor substrate. The well region has a second conductivity type and is configured to form a channel therein under the gate structure during operation. Methods for the fabrication of semiconductor devices are described.

High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The substrate is defined with a device region and a recessed region disposed within the device region. The recessed region includes a recessed surface disposed lower than the top surface of the substrate. A transistor is formed over the substrate. Forming the transistor includes forming a gate at least over the recessed surface and forming a source region adjacent to a first side of the gate below the recessed surface. Forming the transistor also includes forming a drain region displaced away from a second side of the gate. First and second device wells are formed in the substrate within the device region. The first device well encompasses the drain region and the second device well encompasses the source region.

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.

Devices and methods for forming a device are disclosed. The method includes providing a crystalline-on-insulator substrate having a bulk substrate and a surface substrate separated by a buried insulator layer. The surface substrate is defined with a device region. A transistor having a gate is formed in the device region. A first diffusion region is formed adjacent to a first side of the gate and a second diffusion region is formed adjacent to and displaced away from a second side of the gate. At least a first drift isolation region is formed in the surface substrate adjacent to and underlaps the second side of the gate. A drift well is formed in the surface substrate encompassing the first drift isolation region. A device isolation region surrounding the device region is formed in the surface substrate. The device isolation region includes a second depth which is deeper than a first depth of the first drift isolation region.