A semiconductor package in an embodiment includes a semiconductor device which has a first semiconductor element, a second semiconductor element, and a common first electrode between the first and second semiconductor elements. A second electrode is electrically connected to the first semiconductor element. A third electrode extends through the second semiconductor element and electrically connects to the first electrode. A fourth electrode is electrically connected to the second semiconductor element. A first terminal of the package is electrically connected to the third electrode. A second terminal of the package is electrically connected to the second electrode and the fourth electrode. An insulating material surrounds the semiconductor device.

Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.

A lateral superjunction MOSFET device includes multiple transistor cells connected to a lateral superjunction structure, each transistor cell including a conductive gate finger, a source region finger, a body contact region finger and a drain region finger arranged laterally within each transistor cell. Each of the drain region fingers, the source region fingers and the body contact region fingers is a doped region finger having a termination region at an end of the doped region finger. The lateral superjunction MOSFET device further includes a termination structure formed in the termination region of each doped region finger and including one or more termination columns having the same conductivity type as the doped region finger and positioned near the end of the doped region finger. The one or more termination columns extend through the lateral superjunction structure and are electrically unbiased.

A semiconductor device includes a layer having first and second surfaces, a first region including central and peripheral portions, and a second region on the first region. First trenches extend into the first surface and terminate within the first region in the central portion. Each first trench includes a first electrode and a gate electrode over the first electrode. The first and gate electrodes are spaced from the first and second regions by a first insulating layer. A second trench extends into the first surface and terminates within the first region in the peripheral portion. The second trench includes a second electrode and a third electrode over the second electrode. The second and third electrodes are spaced from the first and second regions by a second insulating layer. A fourth electrode overlies the first insulating layer in the central portion and the second insulating layer in the peripheral portion.

A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.

A vertical drift metal-oxide-semiconductor (VDMOS) transistor with improved contact to source and body regions, and a method of fabricating the same. A masked ion implant of the source regions into opposite-type body regions defines the locations of body contact regions, which are implanted subsequently with a blanket implant. The surface of the source regions and body contact regions are silicide clad, and an overlying insulator layer deposited and planarized. Contact openings are formed through the planarized insulator layer, within which conductive plugs are formed to contact the metal silicide, and thus the source and body regions of the device. A metal conductor is formed overall to the desired thickness, and contacts the conductive plugs to provide bias to the source and body regions.

A semiconductor device includes an element portion and a gate pad portion on the same wide gap semiconductor substrate. The element portion includes a first trench structure having a plurality of first protective trenches and first buried layers formed deeper than gate trenches. The gate pad portion includes a second trench structure having a plurality of second protective trenches and second buried layers. The second trench structure is either one of a structure where the second trench structure includes: a p-type second semiconductor region and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer is electrically connected with the source electrode layer.

Provided is a semiconductor apparatus includes: a gate electrode disposed inside a trench and opposedly facing a p type base region with a gate insulating film interposed therebetween on a portion of a side wall; a shield electrode disposed inside the trench and positioned between the gate electrode and a bottom of the trench; an electric insulating region disposed inside the trench, the electric insulating region expanding between the gate electrode and the shield electrode, and further expanding along the side wall and the bottom of the trench so as to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n.sup.+ type source region and the shield electrode, wherein the shield electrode has a high resistance region positioned on an n.sup.+ drain region side, and a low resistance region positioned on a gate electrode side.

Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer formed thereon and of the opposite conductivity type, and a first epitaxial layer formed on mesas of the second semiconductor layer. An electric field along a length of the first epitaxial layer is uniformly distributed.

Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.