A member includes a buffer layer made of GaN. The member is characterized in that the member includes a source layer arranged on top of the buffer layer, and the source layer made of n-doped GaN. The member includes a first barrier layer made of AlGaN arranged over the buffer layer and a first gate layer made of p-doped GaN arranged over the first barrier layer, where the first barrier layer and the first gate layer are arranged adjacent the source layer on one side. The member includes a second barrier layer made of AlGaN arranged over the buffer layer and a second gate layer made of p-doped GaN arranged over the second barrier layer, where the second barrier layer and the second gate layer are arranged adjacent the source layer on another side. The member enables an independent optimization of the two-dimensional electron gas characteristics and the threshold voltage.

The present invention provides an AlGaN/GaN power HEMT device and a preparation method therefor. The device comprises: an n-type GaN substrate, a first p-type GaN layer, an AlGaN layer, a hole-injection-type PN junction layer and a gate structure, wherein the gate structure penetrates the hole-injection-type PN junction layer, the AlGaN layer and the first p-type GaN layer and stops in the n-type GaN substrate, and comprises a gate metal aluminum layer and a gate silicon dioxide layer; and the hole-injection-type PN junction layer comprises a second p-type GaN layer and a second n-type GaN layer, which are distributed in the horizontal direction, and the second n-type GaN layer is located on the side close to the gate structure.

A HEMT device including: a semiconductor body forming a heterostructure; a gate region on the semiconductor body and elongated along a first axis; a gate metal region including a lower portion on the gate region and recessed with respect to the gate region, and a upper portion on the lower portion and having a width greater that the lower portion along a second axis; a source metal region extending on the semiconductor body and made in part of aluminum; a drain metal region on the semiconductor body, the source metal region and the drain metal region on opposite sides of the gate region; a first conductivity enhancement region of aluminum nitride, extending on the semiconductor body and interposed between the source metal region and the gate region, the first conductivity enhancement region being in direct contact with the source metal region and being separated from the gate region.

A heterojunction power device includes: a substrate containing semiconductor material; a first active area and a second active area, arranged on the substrate symmetrically opposite with respect to an axis of symmetry and accommodating respective heterostructures; a separation region, extending along the axis of symmetry between the first active area and the second active area. The power device further includes: a first conductive bus configured to distribute a first electric potential of the power device in parallel to the first and the second active areas; a second conductive bus configured to distribute a second electric potential of the power device, different from the first electric potential, in parallel to the first and the second active areas. The first and the second conductive buses extend along the axis of symmetry above the separation region and the second conductive bus overlies the first conductive bus.

The present disclosure generally relates to integrated devices with a conductive barrier structure. In an example, a semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, a gate, and a conductive structure. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is of a second semiconductor material and is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The gate is over the barrier layer opposing the channel layer. The conductive structure is electrically coupled between the conductive barrier structure, the channel layer, and the barrier layer.

Disclosed herein are approaches for creating high electron mobility transistors with reduced contact resistance. In one approach, a method of forming a semiconductor device may include applying a first patterned mask on top of layered stack, wherein the layered stack includes a substrate, a buffer layer disposed over the substrate, a channel layer disposed above the buffer layer, and a barrier layer disposed above the channel layer. The method may further include forming, through an opening of the patterned mask, a source/drain contact in the barrier layer by delivering a first implant to the layered stack, and performing an etch process to form a contact opening in the source/drain contact. The method may further include performing a second implant to the source/drain contact, wherein the second implant is directed into the contact opening.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate comprising a first oxide material; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.

A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a buffer layer on the substrate, forming a mesa isolation on the HEMT region, forming a HEMT on the mesa isolation, and then forming a capacitor on the capacitor region. Preferably, a bottom electrode of the capacitor contacts the buffer layer directly.

A semiconductor device has a first region and a second region including a first structural layer, a second structural layer, first electrode structure and second electrode structure. The material of the first structural layer comprises monocrystalline diamond, and a portion of the first structural layer located in the first region is electrically isolated from a portion located in the second region. The second structural layer is disposed on the first structural layer, and located in the first region, and forms a heterojunction structure with the first structural layer; the material of the second structural layer includes a monocrystalline AlN film or a doped monocrystalline AlN film. The first electrode structure comprises a first source electrode, a first gate electrode and a first drain electrode. The second electrode structure comprises a second source electrode, a second gate electrode and a second drain electrode.