The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP comprises portions of a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. The MIMCAP comprises a bottom plate formed in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate formed in the second metallization layer, on and in electrical contact with the second metal plate. The electrical contacts to the bottom and top plates of the MIMCAP formed in the first and second metallization layer are thereby established without forming separate vias between the plates and the metallization layers. In addition, the first conductive layer of the MIMCAP may extend beyond the surface of the dielectric and the second layer for forming other structures.

An electronic component includes a body part and a via part. The body part includes first and second metal layers disposed with at least one dielectric layer interposed therebetween. The via part is disposed in the body part and includes first and second vias penetrating through the body part and selectively connected to the first and second metal layers, respectively. The first and second metal layers contain different metals. In some examples, a first insulating film is disposed between the first metal layer and the second via to electrically insulate the second via from the first metal layer, and a second insulating film is disposed between the second metal layer and the first via to electrically insulate the first via from the second metal layer. A method for forming the electronic component includes use of first and second etchants to selectively etch the first and second metal layers.

A chip resistor has a substrate, a first connection electrode and a second connection electrode that are formed on the substrate, and a resistor network that is formed on the substrate and that has ends one of which is connected to the first connection electrode and the other one of which is connected to the second connection electrode. The resistor network is provided with a resistive circuit. The resistive circuit has a resistive element film line that is provided along inner wall surfaces of trenches. The resistive element film line extending along the inner wall surfaces of the trenches is long and has a high resistivity as a unit resistive element.

The invention provides transient devices, including active and passive devices that electrically and/or physically transform upon application of at least one internal and/or external stimulus. Materials, modeling tools, manufacturing approaches, device designs and system level examples of transient electronics are provided.

An apparatus having a power converter circuit having a first active layer having a first set of active devices disposed on a face thereof, a first passive layer having first set of passive devices disposed on a face thereof, and interconnection to enable the active devices disposed on the face of the first active layer to be interconnected with the non-active devices disposed on the face of the first passive layer, wherein the face on which the first set of active devices on the first active layer is disposed faces the face on which the first set of passive devices on the first passive layer is disposed.

A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties.

A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.

Embodiments include a random number generation entity having at least one switching cell comprising a pair of electrodes and a chalcogenide layer arranged between the pair of electrodes and a pulse generating entity coupled with the electrodes of the switching cell. The pulse generating entity is configured to provide an excitation pulse to the switching cell. The random number generation entity also includes a detection entity configured to provide a detection signal indicating whether an electrical property measured at the switching cell exceeds or falls below a threshold value due to applying the excitation pulse to the switching cell and a random number generation entity adapted to generate a random number based on the detection signal of the detection entity.

A capacitor includes an elevationally inner capacitor electrode, an elevationally outer capacitor electrode, and capacitor insulator between the elevationally inner and outer capacitor electrodes. The elevationally inner capacitor electrode comprises a hollow longitudinally-elongated conductive cylinder-like portion and a non-hollow longitudinally-elongated conductive cylinder-like portion electrically coupled with the hollow cylinder-like portion. The non-hollow cylinder-like portion is radially of and extends longitudinally along a longitudinal side surface of the hollow cylinder-like portion. Additional embodiments and aspects are disclosed.

The purpose of the invention is to form a stable oxide semiconductor TFT in a display device. The concrete structure is: A display device having a TFT substrate that includes a TFT having an oxide semiconductor layer comprising: the oxide semiconductor layer is formed on a first insulating film that is formed by a silicon oxide layer, the oxide semiconductor layer and an aluminum oxide film are directly formed on the first insulating film. The first insulating film becomes oxygen rich when the aluminum oxide film is formed on the first insulating film by sputtering. Oxygens in the first insulating film is effectively confined in the first insulating film, eventually, the oxygens diffuse to the oxide semiconductor for a stable operation of the oxide semiconductor TFT.