A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.

Aspects of the present disclosure provides a device comprising a P-type semiconductor substrate, an N-type tub above the semiconductor substrate, a P-type region provided in the N-type tub isolated by one or more P-type isolation structures, and an N-type punch-through stopper provided under the P-type regions isolated by the isolation structure(s). The punch-through stopper is heavily doped compared to the N-type tub. The P-type region has a width between the two isolation structures that is equal to or less than that of the N-type punch-through stopper.

A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.

A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.

A semiconductor structure includes a bulk semiconductor substrate, an electrically insulating layer over the substrate, an active layer of semiconductor material over the electrically insulating layer and a transistor. The transistor includes an active region, a gate electrode region and an isolation junction region. The active region is provided in the active layer of semiconductor material and includes a source region, a channel region and a drain region. The gate electrode region is provided in the bulk semiconductor substrate and has a first type of doping. The isolation junction region is formed in the bulk semiconductor substrate and has a second type of doping opposite the first type of doping. The isolation junction region separates the gate electrode region from a portion of the bulk semiconductor substrate other than the gate electrode region that has the first type of doping.

A semiconductor device includes an isolation layer, first and second fin structures, a gate structure and a source/drain structure. The isolation layer is disposed over a substrate. The first and second fin structures are disposed over the substrate, and extend in a first direction in plan view. Upper portions of the first and second fin structures are exposed from the isolation layer. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The source/drain structure is formed on the upper portions of the first and second fin structures, which are not covered by the first gate structure and exposed from the isolation layer, and wraps side surfaces and a top surface of each of the exposed first and second fin structures. A void is formed between the source/drain structure and the isolation layer.

Present embodiments provide for a complementary nanowire semiconductor device and fabrication method thereof. The fabrication method comprises providing a substrate, wherein the substrate has a NMOS active region, a PMOS active region and a shallow trench isolation (STI) region; forming a plurality of first hexagonal epitaxial wires on the NMOS active region and the PMOS active region by selective epitaxially growing a germanium (Ge) crystal material; selectively etching the substrate to suspend the pluralities of first hexagonal epitaxial wires on the substrate; forming a plurality of second hexagonal epitaxial wires on the NMOS active region by selective epitaxially growing a III-V semiconductor crystal material surrounding the pluralities of first hexagonal epitaxial wires on the NMOS active region; depositing a dielectric material on the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the dielectric material covers the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires; and depositing a conducting material on the dielectric material for forming a gate electrode surrounding the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the pluralities of first hexagonal epitaxial wires are a plurality of first nanowires and the pluralities of second hexagonal epitaxial wires are a plurality of second nanowires.

A method of fabricating a semiconductor structure includes forming an isolation feature in a substrate, removing a portion of the isolation feature and a portion of the substrate underneath the removed portion of the isolation feature to form a trench in the substrate, and forming a trapping feature around a bottom portion of the trench. A first sidewall and a second sidewall of the trench are in direct contact with the isolation feature, and a bottom surface of the trench is below a bottom surface of the isolation feature.